Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-15
2005-02-15
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S296000, C438S424000, C438S673000, C438S701000
Reexamination Certificate
active
06855591
ABSTRACT:
A nonvolatile memory device and a method of forming the nonvolatile memory device having a shallow trench isolation structure and having a device isolation layer having a protruding portion above a substrate surface includes forming a gate oxide, a lower conductive layer pattern, and a hard mask layer; patterning the hard mask layer; isotropically etching the lower conductive layer to form a lower conductive layer pattern having a sloped sidewall profile where a width of a lower portion of the lower conductive layer pattern is smaller than a width of an upper portion of the lower conductive layer pattern; etching the gate oxide layer and the substrate, using the hard mask pattern as an etch mask, to form a trench; and forming a device isolation layer contacting with a sidewall of the lower conductive layer pattern in the trench.
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Aritome et al. a 0.67 Self-Aligned Shallow Trench Isolation Cell, etc., 1994, 3.6.1-3.6.4., ULSI Research Labs.).
Fourson George
Garcia Joannie Adelle
Lee & Sterba, P.C.
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