Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-28
2001-07-03
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S350000, C365S053000, C365S182000, C365S185270, C365S185280, C365S185290, C365S218000
Reexamination Certificate
active
06255166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory cell, a method of programming the same and non volatile memory array and more particularly to the nonvolatile memory cell enabling low voltage programming and/or high speed programming, a method of programming same and nonvolatile memory array.
2. Description of the Related Art
A MNOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MNOS memory is of a laminated structure comprising a conductive gate (M), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge. In this step, the silicon nitride film of the MNOS memory was required to be more than 19 nm in thickness since the charge trapping efficiency depended on the carrier capture distance in the silicon nitride film as described in F. L. Hampton and J. R. Cricchi “Space Charge Distribution Limitation of Scale Down of MNOS Devices”, 1979 IEDM Technical Digest p. 374. To program (write or erase) the MNOS memory, at least more than 10V or about 20V as a normal value of programming voltage was required for a electric field to be fed to a semiconductor surface via the silicon nitride film so that a carrier may be injected in the nitride film through (via a tunnel) the tunnel oxide film.
A MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage by E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, “A Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structures”, in IEEE Transaction on Electron Devices, Vol. ED-30, February, 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner.
This MONOS memory has made it possible to reduce the programming voltage down to 9V with the usable programming speed (0.1 msec) under the condition that the stored information is maintained for ten years as indicated in T. Nozaki, T. Tanaka. Y. Kijiya, E. Kinoshita, T. Tsuchiya and Y. Hayashi, “A1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application”, IEEE Journal of Solid-State Circuits, Vol.
26
, No.4, April, 1991, p. 497).
It has yet to be disclosed, however, whether or not it is possible to reduce programming voltage to be less than 9V under the condition that the programming speed is less than 0.1 msec and memory retention characteristics is maintained. To achieve the programming voltage of less than 9V, either programming speed or memory storage characteristics or both were required to be sacrificed.
On the other hand, PAC (perpendicularly accelerated channel) injection is disclosed as a method to improve the injection efficiency to the gate insulator with the programming voltage being lowered as seen in M. Kamiya, Y. Kojima. Y. Kato, K. Tanaka and Y, Hayashi, “EEPROM with High Gate Injection Efficiency”, 1982 IEDM technical Digest, 30.4, p741.
To achieve the PAC injection, a first conductive gate is disposed on a channel forming region at the source side via a gate insulator and a floating gate, on the channel forming region at the drain side. A carrier supplied from the source side to a surface of the channel forming region is once pushed from the surface to inside of the channel forming region at a drain side end portion of the first conductive gate and again drawn to the channel forming region under the floating gate. In this step, part of the carrier drawn thereto is injected in the floating gate getting over a potential barrier between the gate insulator and channel forming region surface. To have the carrier injected therein, it is required that the potential difference between the channel forming region and drain region be more than the height of the potential barrier (V
b
) (The potential from the outside is V
B
-2□
F
2
; 2□
F
2
is a Fermi-level in the channel forming region.).
The PAC injection enables high speed and low current programming since the injection efficiency (the ratio of a carrier current to be injected to the current flowing in a channel) is high (about three orders of magnitude improvement was observed compared to the conventional channel hot electron injection [CHE injection]).
It has recently been found that the critical film thickness of the gate insulator under the floating gate is 8 nm. “Thinning a tunnel oxide film reaches its limit at 8 nm . . . Limit to a large capacity flush memory” by S. Lai, disclosed at page 70 in “Nikkei Microdevice” published in April, 1967. The carrier injection is achieved in such a step that a control gate (or a drain gate in stead of a control gate) is capacitance-coupled with the floating gate via the insulator to control the floating gate potential, but the equivalent insulator thickness measured from the control gate becomes about twice that of the critical value. Accordingly, the control gate voltage during the programming is limited by the equivalent film thickness causing a limit to making the programming voltage lower.
Compared to the MNOS memory, the MONOS memory has achieved to some extents low voltage programming, but has problems to be resolved in terms of further reducing the programming time and realizing the lower voltage programming.
SUMMARY OF THE INVENTION
It is a purpose of the present invention to provide a nonvolatile memory cell capable of programming not only at a higher speed and with lower voltage compared to a MNOS memory but also with lower voltage compared to a conventional floating gate memory; and a method of programming the same and a high density nonvolatile memory array.
To achieve the purpose as described, the present invention is provided with the means featured below.
(1) A pair of source and drain regions formed in a main surface of a substrate and separated by channel forming regions therebetween; a first gate insulator formed on a surface of a first channel forming region adjacent to the source region out of the channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to the drain region out of the channel forming regions; a first gate electrode formed on the first gate insulator; and a second gate electrode formed on the second gate insulator, wherein the second insulator includes a first layer forming a potential barrier at the interface with the channel forming region; a third layer forming the potential barrier at the interface with the second gate electrode and the second layer forming the carrier trapping level at least a location out of the interfaces between the second layer and the first layer or the third layer and a location in the second film itself.
(2) A first potential feeding means which feeds to the drain region the first potential to supply to the carrier such energy as the carrier is capable of getting over the potential barrier formed between the second channel forming region and first layer of the second gate insulator; and a second potential feeding means which feeds to the second gate electrode a potential to form an auxiliary electric field capable of having the carrier having overcome the potential barrier reached the second layer of the second gate insulator.
(3) A pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming s
Hayashi Yutaka
Ogura Seiki
Aalo LSI Design & Device Technology, Inc.
Ackerman Stephen B.
Le Vu A.
Luu Pho
Pike Rosemary L. S.
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