Nonvolatile memory and nonvolatile memory apparatus

Details Nonvolatile memory and nonvolatile memory apparatus Nonvolatile memory and nonvolatile memory apparatus

2007-12-04

2007-12-04

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S746000, C714S764000, C714S799000, C714S810000, C714S048000, C714S723000, C714S733000, C714S734000, C365S185090, C365S185330

Reexamination Certificate

active

11182781

ABSTRACT:
To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.

REFERENCES:
patent: 5559956 (1996-09-01), Sukegawa
patent: 6185134 (2001-02-01), Tanaka
patent: 6982904 (2006-01-01), Shiga
patent: 7184356 (2007-02-01), Noguchi et al.
patent: 2004/0156251 (2004-08-01), Shiota et al.
patent: 2005/0180211 (2005-08-01), Guterman et al.
patent: 2004-240793 (2004-08-01), None

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