Nonvolatile memory

Details Nonvolatile memory Nonvolatile memory

2000-03-21

2003-09-23

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000, C438S257000

Reexamination Certificate

active

06624026

ABSTRACT:

BACKGROUND
This invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off. There are several different types of nonvolatile memories including erasable programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories. EPROMS are erasable through light exposure but are electrically programmable by channel hot electron injection onto a floating gate. Conventional EEPROMs have the same programming functionality, but instead of being light erasable they can be erased and programmed by electron tunneling facilitated by an on-chip electrical signal. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques. Flash EEPROMs may be block erased, typically giving them better read access times than regular EEPROMs.
Currently, flash memories have gained considerable popularity. For example, flash memories are often utilized to provide on-chip memory for microcontrollers, modems and SMART cards and the like where it is desirable to store codes that may need fast updating.
While flash memories and EEPROMs are closely related, in many instances, flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
Nonvolatile memory cells differ in certain respects from the transistors that are generally utilized in electronic components called logic devices, such as microcontrollers, that work with the memory cells. Logic devices are formed of transistors that use a single gate electrode. Nonvolatile memories usually include two gate electrodes, known as the control and floating gate electrodes, situated one adjacent to the other. Because of this structural difference, nonvolatile memories and logic devices may be made by different processes. This may contribute to a substantial increase in process complexity and manufacturing cost when the two components need to be placed together into the same chip.
Particularly with an EEPROM, the electrical programming of the cells normally requires substantial potentials to be applied to the cells. These potentials induce electron tunneling from an N+ region onto the floating gate. Additional complexity may arise from the need to provide substantially larger voltages to memory cells than are needed for normal logic transistor operation.
While the industry has come to accept the need for separate process technologies for logic and nonvolatile memories and while those in the industry have also come to appreciate that significant currents are needed to program flash EEPROMS, there would be a substantial demand for a nonvolatile memory which was both electrically erasable and programmable without the need for special process technologies or for relatively higher programming voltages and higher currents.
Furthermore, with the conventional flash EEPROMs, the electrical programming of the cells normally requires high current to be applied to the cells. A very minute fraction of this electron current becomes injected from the drain depletion region onto the floating gate. This means that the injection efficiency of such devices is low (e.g., 1×10
−6
to 1×10
−9
). The requirement of high current adds additional complexity because of the design of the high current pump operated at low voltage.
SUMMARY
In accordance with one embodiment, a memory array including word lines and bit lines includes a first and second cell, each having a control gate, floating gate and a source formed in a substrate. The control gate is situated over the floating gate. The cells are each adapted to form a depletion region in the substrate. A drain is situated between the first and second cells, each of the cells being part of a different word line.
Other aspects are set forth in the accompanying detailed description and claims.


REFERENCES:
patent: 4639893 (1987-01-01), Eitan

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