Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-15
2001-06-05
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S317000
Reexamination Certificate
active
06242303
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacture process, and more especially, to a method for increasing capacitive-coupling ratio of a electrically erasable programmable memory.
BACKGROUND OF THE INVENTION
In the early years of electric and semiconductor industry, traditional programmable semiconductor devices are developed for nonvolatile memories to rewrite the data stored. Nonvolatile memories, including mask read-only memories (Mask ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM or E
2
PROM) and flash memories, retain their memory data whenever the power is turned off, and have wide applications in the computer and electronic industry. In recent years, erasable programmable logic devices (EPLDs) are also developed to produce semi-manufactured products before order and reduce the period between order and delivery. With the erasable programmable logic devices, standard logic arrays can be fabricated in advance, and the final connections of devices are made in accordance with customer specification. Such an erasable programmable logic device has a programming mechanism all the same to an electrically erasable programmable memory.
FIG. 1
shows a traditional structure of an erasable programmable logic device or an electrically erasable programmable memory. In this structure, there are active area
12
, floating gate
14
, control gate
18
, and select gate
24
, also the tunnel window
16
formed between the active area and the floating gate, source region
20
(only the contact window labeled), and drain region
22
(only the contact window labeled). Cross section AA′ is shown in
FIG. 2
, wherein isolation regions of field oxide (FOX)
30
, tunnel oxide
16
and non-tunnel oxide
32
between active area and the floating gate, inter-poly dielectric
34
between floating and control gates, and inter layer dielectric (ILD)
36
on floating gate, are formed.
The basic storage cell of these programmable and erasable memories contains a double polysilicon storage transistor with a floating gate isolated in silicon dioxide and capacitively coupled to a second control gate. These memories execute the program and erasure by charging or discharging their floating gates. For example, the EPROM is programmed by hot electron injection at the drain to selectively charge the floating gate and erased by discharging the floating gate with ultraviolet light or X-ray. The E
2
PROM and most of the flash memories are programmed by hot electron injection or cold electron tunneling named Fowler-Nordheim tunneling, and erased mostly by. Fowler-Nordheim tunneling from the floating gate to the source, with the control gate ground.
Fowler-Nordheim tunneling, or named cold electron tunneling, is a quantum-mechanical effect, which allows the electrons to pass through the energy barrier at the silicon-silicon dioxide interface at a lower energy than required to pass over it. Because of its low current consumption, the Fowler-Nordheim program/erase scheme becomes indispensable for low power operation of the E
2
PROM and flash memories. But the Fowler-Nordheim program/erase scheme requires high voltage that applied to control gate of the memory cell due to its need for a large reversible electric field to the thin oxide separating the floating gate from the substrate. Therefore, to lower the control gate bias, the memory cell must have a high capacitive-coupling ratio structure.
Capacitive-coupling ratio is defined as the ratio of the capacitance between control and floating gates to the total capacitance of floating gate, also the ratio of the bias of the floating gate to that of the control gate. The total capacitance of floating gate is the capacitance between control and floating gates in addition to the capacitance between floating gate and source region. As its definition, the higher the capacitive-coupling ratio is, the higher the induce bias of floating gate is, wherein the latter is induced by the supplied bias of the control gate. In the other words, applying a same control bias, the induced bias of floating gate is higher as the capacitive-coupling ratio is, as well as the efficiency of the device. Therefore, there is a demand to increase the capacitive-coupling ratio for the manufacture of device with low power consumption and high operation efficiency.
Typically, for a standard capacitor, the capacitance C=k∈
o
A/d, wherein A is the coupling area of the conductive layer, ∈
o
is the permittivity of vacuum, d is the thickness of the dielectric layer, and k is the permittivity of the dielectric material employed. In general, there is a lower thickness limit of the inter-poly dielectric between control and floating gate to prevent the occurrence of tunnel. Therefore, the most ideal way to increase the capacitive-coupling ratio is to increase the coupling area between control gate and floating gate. However, as the semiconductor manufacture tend to increase integration of device, the area allowed for a device is decreased day by day. Therefore, it will be a challenge to increase capacitive-coupling ratio in such a decreased device area.
SUMMARY OF THE INVENTION
The present invention proposes a novel method for manufacturing an erasable programmable memory, which utilizes the enlargement of the coupling area between control and floating gates to increase the capacitive-coupling ratio. Firstly, the isolation regions are formed on the substrate to define active areas. A silicon oxide mask is formed on the substrate to cover the tunnel region and expose the control region. A polysilicon layer is subsequently formed on the substrate.
A photoresist is then patterned on the polysilicon layer to cover a portion of the control region and expose the other regions. An anisotropic etching is then performed to pattern the polysilicon layer using the patterned photoresist as a mask. Only the portion of the polysilicon layer on the control region and covered by the photoresist remains. An over etching using the same pattern is selectively performed to etch the exposed portion of the substrate on the control region. After the patterned photoresist is removed and wet cleaned, the oxide mask is stripped, and an uneven silicon surface with protrusions and recesses is thus formed on the control region.
Subsequently, an ion implantation is carried out to implant impurity dopants into the substrate and form the doped tunnel region and the control gate. The control gate consists of the doped polysilicon layer and the doped control region in the substrate. A first silicon oxide layer is then grown on the substrate, the portion of the first silicon oxide layer on the control region is removed, and the portion of the first silicon oxide layer on the surface of tunnel region remains.
Thereafter, a second silicon oxide layer is formed on the substrate. At this moment, there is only this second silicon oxide layer on the control region, but the first and second silicon oxide layers lying on the tunnel region. The second silicon oxide layer is thinner the first silicon oxide layer. Another photoresist is patterned and tunnel window is defined on the tunnel region. The portions of the first and second silicon oxide layers on the tunnel window are removed. The portions of the first and second silicon oxide layers that are not on the tunnel window remain.
A third silicon oxide layer is then formed on the substrate. At this moment, there is only the third silicon oxide layer on the tunnel window to serves as tunnel oxide layer. On the tunnel region other than the tunnel window, the first, second and third silicon oxide layers lie to serve as the non-tunnel oxide layer. On the control region, the second and third silicon oxide layers lie to serve as the inter-poly dielectric. The third silicon oxide layer is also thinner than the first silicon oxide layer.
A floating gate is now deposited on the tunnel region and most area of the control region. On the floating gate, an inter-layer dielectric is formed to s
Liu Chia-Chen
Wang Ling-Sung
Wilson Christian D.
Worldwide Semiconductor Manufacturing Corp.
Zarabian Amir
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