Nonvolatile floating-gate memory devices, and process of...

Details Nonvolatile floating-gate memory devices, and process of... Nonvolatile floating-gate memory devices, and process of...

2000-04-13

2002-09-10

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06448138

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a process of fabricating floating-gate memory devices, and to a memory device fabricated thereby.
BACKGROUND OF THE INVENTION
As is known, the fabrication of nonvolatile floating-gate memory devices comprises a sequence of steps commencing with a substrate of semiconductor material (monocrystalline silicon). More specifically, according to a typical fabrication process, a gate oxide layer is grown on the substrate, in which the active areas and any P- and N-wells required according to the process are already defined. A thin tunnel oxide region is possibly grown in the gate oxide layer (as in the case of EEPROM memories). A first polycrystalline silicon layer (poly1) is deposited and patterned to define it in a first, channel width direction on the oxide layers. An intermediate dielectric layer of silicon oxide or ONO—an acronym of silicon Oxide-silicon Nitride-silicon Oxide, is deposited or grown thermally on poly1. A second polycrystalline silicon layer (poly2) is deposited on the dielectric layer. A tungsten silicide layer is possibly deposited on poly2. The stack of poly2, ONO and poly1 layers is self-align etched to define the stacked floating and control gate regions in a second, channel-length direction perpendicular to the first direction. Next, the source/drain regions of the cell are implanted. A “reoxidation” heat treatment is performed to seal the floating gate region. Now, the source and drain regions of peripheral circuit transistors are formed and reoxidized. And finally, the contacts and interconnecting layer are formed and a passivation layer is deposited.
One of the most critical steps in the above process, regardless of the architecture being formed, is the reoxidation step. The reoxidation step, as stated, provides for sealing the floating gate region of the cells to prevent direct contact with the outside environment, ensure long-term retention of the charge stored in the region, and so ensure good quality of the memory even in the event of prolonged operation.
The reoxidation step may also serve other purposes. First, this step helps in stabilizing the tungsten silicide layer which may form part of the control gates of the devices, including both the cells and the circuit transistors. Second, the reoxidation step provides for diffusing in the substrate the normally implanted dopant that determines the electric characteristics of the devices.
It is desired that the reoxidation step be made as effective as possible to insure the insulation and charge retention of nonvolatile memories.
To improve the electric characteristics of transistors, an article entitled “Suppression of MOSFET Reverse Short Channel Effect by N
2
O Gate Poly Reoxidation Process” by P.G.Y. Tsui, S. H. Tseng, M. Orlowski, S. W. Sun, P. J. Tobin, K. Reid and W. J. Taylor, IEDM 94, 19.5.1, proposes, during final reoxidation of the gate region, to use a gas for nitriding the interface between the silicon substrate and gate oxide, at least in the areas closest to the exposed sides of the transistor. In particular, oxinitriding is aimed at eliminating the reverse short channel effect (i.e., the increase in the threshold voltage of short channel MOSFET transistors) generally attributed to an uneven lateral channel profile caused, among other things, by reoxidation resulting in the formation of supersaturated silicon interstitial.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fabrication process enabling improved insulation of the floating gate of nonvolatile floating-gate memory devices.
According to the present invention, there is provided a process of fabricating floating-gate memory devices. More specifically, on a substrate, an insulated control gate region is formed on a floating gate region. Next, an insulating layer of oxynitride is formed on the side of the floating gate region.


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