Nonvolatile ferroelectric random access memory device with...

Details Nonvolatile ferroelectric random access memory device with... Nonvolatile ferroelectric random access memory device with...

2000-06-12

2001-03-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S230030

Reexamination Certificate

active

06201727

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to random access memory devices and, more particularly, to a nonvolatile ferroelectric random access memory device with a segmented plate line and a method for driving a plate line segment therein.
BACKGROUND OF THE INVENTION
A ferroelectric random access memory uses a ferroelectric capacitor as the storage element for each memory cell. Each memory cell stores a logic state based on the electrical polarization of the ferroelectric capacitor. The ferroelectric capacitor has a dielectric between its plates (or electrodes) that comprises a ferroelectric material such as lead zirconate titanate (PZT). When a voltage is applied to the plates of the ferroelectric capacitor, the ferroelectric material is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor is defined as the coercive voltage. One plate of the ferroelectric capacitor is coupled to a bit line via an access transistor and the other plate is coupled to a plate line (or drive line) as disclosed in U.S. Pat. No. 5,751,626, entitled “FERROELECTRIC MEMORY USING FERROELECTRIC REFERENCE CELLS” incorporated herein by reference.
The ferroelectric capacitor exhibits hysteresis. The flow of current to the capacitor depends on its polarization state. If the voltage applied to the capacitor is greater than its coercive voltage, then the ferroelectric capacitor may change the polarization state depending on the polarity of the applied voltage. The polarization state is retained after power is removed resulting in nonvolatility. The ferroelectric capacitor can be switched between polarization states in about one nanosecond, which is faster than the programming time of most other nonvolatile memories such as Erasable Programmable Read Only Memories (EPROMs), Electrically Erasable Programmable Read Only Memories (EEPROMs) or flash EEPROMs.
In order to read or write data from or to a memory cell, respectively, the plate line is driven such that a voltage difference between the plates of the ferroelectric capacitor is applied. Circuits for driving plate lines are disclosed in U.S. Pat. No. 5,592,410, entitled “CIRCUIT AND METHOD FOR REDUCING A COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION” and U.S. Pat. No. 5,086,412, entitled “SENSE AMPLIFIER AND METHOD FOR FERROELECTRIC MEMORY,” which are hereby incorporated by reference. Both of these U.S. patents disclose an array of memory cells and a decoder that is coupled to the array via a plurality of word lines and a plurality of plate lines corresponding to the word lines, respectively. According to the decoding structure of the above-described patents, a word and a plate line are simultaneously selected and driven by the decoder. However, the above described decoding structure is inapt to the high density memory device because the number of ferroelectric capacitors commonly coupled to a plate line is limited owing to the high RC delay of the plate line.
One solution to the above-mentioned problem is termed “segmented plate line” structure. The segmented plate line structure is disclosed in U.S. Pat. No. 5,598,366, entitled “FERROELECTRIC NONVOLATILE RANDOM ACCESS MEMORY UTILIZING SELF-BOOSTING PLATE LINE SEGMENT DRIVERS” and U.S. Pat. No. 5,373,463, entitled “FERROELECTRIC NONVOLATILE RANDOM ACCESS MEMORY HAVING DRIVE LINE SEGMENTS,” which are hereby incorporated by reference.
According to the segmented plate line structure disclosed in the '366 and '463 patents, changes in the polarization state of memory cells coupled to inactive plate line segments are eliminated, reducing fatigue and extending the useful operating life of the memory device. Additionally, the segmented plate line structure reduces total power consumption of the memory array and the time required to transition a plate line segment when compared to a non-segmented plate line.
In the segmented plate line structure, deselected plate line segments are floated during a write/read operation. Because of this they are exposed to peripheral noise and signal coupling. That is, the deselected plate line segments are electrically coupled to selected bit lines and to a selected plate line segment. Therefore, the polarization direction of the ferroelectric capacitors coupled to the deselected plate line segments may be changed during the read/write cycle associated with the selected plate line segment. This coupling causes the reduction of the sensing margin and the destruction of data that is stored in the ferroelectric capacitors coupled to the deselected plate line segments.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a nonvolatile ferroelectric random access memory device having a segmented plate line structure that is capable of preventing deselected plate line segments from floating during a read/write cycle and to provide a method for driving a plate line segment therein.
In order to attain the above objects, according to an aspect of the present invention, there is provided a ferroelectric random access memory device that comprises a word line arranged in a first direction, a plate line arranged in the first direction, a plurality of bit lines arranged in a second direction perpendicular to the first direction, and a plurality of memory cells each arranged at an intersection of the word line and a cororesponding bit line. A first and a second switch circuit are further provided. The first switch circuit couples one end of the plate line to the word line responsive to a first switch control signal. The first switch circuit comprises an NMOS transistor having a gate for receiving the first switch control signal and a current path formed between the word line and the plate line. The second switch circuit couples the other end of the plate line to a reference voltage responsive to a second switch control signal. The second switch circuit comrprises an NMOS transistor having a gate for receiving the second switch control signal and a current path formed between the plate line and the reference voltage.
According to the present invention, the ferroelectric random access memory device further comprises a second plurality of bit lines arranged in the second direction, a second plate line arranged in the first direction and isolated from the first plate line, and a second plurality of memory cells, each memory cell of the second plurality of memory cells being at an intersection of the word line and a corresponding second bit line, a third switch circuit for coupling one end of the second plate line to the word line responsive to a third switch control signal, and a fourth switch circuit for coupling the other end of the second plate line to the ground voltage responsive to a fourth switch control signal.
The third switch control signal comprises a third NMOS transistor having a gate for receiving the third switch control signal and a current path formed between the word line and the second plate line. The fourth switch circuit comprises of a fourth NMOS transistor having a gate for receiving the fourth switch control signal and a current path formed between the second plate line and the ground voltage.
According to another aspect of this invention, there is provided a method for driving a plate line in a ferroelectric random access memory device, the ferroelectric random access memory having a memory cell array including a word line arranged in a row direction, a plate line arranged in the row direction, a plurality of bit lines arranged in a column direction, and a plurality of memory cells, each memory cell arranged respectively at the intersection of the word line and a corresponding bit line. The method comprises charging the plate line with a reference voltage, decoupling the plate line from the reference voltage, coupling the word line and the plate line after decoupling the plate line, and activating the word line so that the plate line has a plate line voltage.


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