Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-04-10
2001-05-22
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S210130
Reexamination Certificate
active
06236588
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-30873, filed on Jul. 28, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a nonvolatile ferroelectric random access memory device and a related data reading method.
BACKGROUND OF THE INVENTION
A ferroelectric random access memory (hereinafter, referred to as an “FPAM”) uses a ferroelectric capacitor as a storage element for each of a plurality of memory cells. Each memory cell stores a logic value based on the electrical polarization of the ferroelectric capacitor. The ferroelectric capacitor includes two electrodes (or plates) and a dielectric between the two electrodes that comprises a ferroelectric material such as lead zirconate titanate (PZT). When a voltage is applied across the electrodes of the ferroelectric capacitor, the ferroelectric material is polarized in the direction of the electric field. The switching threshold voltage for changing the polarization state of the ferroelectric capacitor is defined as the coercive voltage.
If the voltage applied to the capacitor is greater than its coercive voltage, then the ferroelectric capacitor may change its polarization state depending upon the polarity of the applied voltage. The FRAM retains its polarization state after power is removed, thus providing nonvolatility in the FRAM memory device. The ferroelectric capacitor can be switched between polarization states in about one nanosecond, which is faster than the programming time of most other nonvolatile memories such as Erasable Programmable Read Only Memories (EPROMs), Electrically Erasable Programmable Read Only Memories (EEPROMs), or flash EEPROMs.
In an FRAM memory device, a first electrode of the ferroelectric capacitor is coupled to a bit line via an access transistor and a second electrode of the ferroelectric capacitor is coupled to a plate line (or drive line), as is disclosed in U.S. Pat. No. 5,751,626, entitled “FERROELECTRIC MEMORY USING FERROELECTRIC REFERENCE CELLS”, which is hereby incorporated by reference in its entirety.
FIG. 1
is a graph showing a hysterisis I-V switching loop of a ferroelectric capacitor. In this graph, the abscissa indicates a potential difference between both electrodes of the ferroelectric capacitor, i.e., a voltage between the two electrodes of the capacitor, and the ordinate indicates the amount of charge induced at a surface of the ferroelectric material in accordance with spontaneous polarization, i.e., the degree of polarization (&mgr;C/cm
2
). In the FRAM, a binary data signal corresponds to the points B and D of the hysterisis loop shown in FIG.
1
. Logical “one” (“1”) corresponds to point B, and logical “zero” (“0”) corresponds to point D. A read operation of the FRAM will be described below with reference to FIG.
1
.
At an initial stage of the read operation of the FRAM, an operation for sensing data stored in memory cells is carried out. Before the sensing operation, a bit line coupled to a memory cell is grounded. Then, during the sensing operation, the bit line is maintained in a floating state. The access transistor of the memory cell is then turned on by a word line so that the zero voltage on the bit line is applied to a first electrode of the corresponding ferroelectric capacitor, and a pulse signal of, for example, V
cc
level is applied to the second electrode of the ferroelectric capacitor. At this time, if a logical data “1” is stored in the ferroelectric capacitor, the degree of polarization of the capacitor is varied from the point B to the point D through the point C. As a result, a charge amount of dQ
1
is transmitted from the ferroelectric capacitor to the bit line, and thereby the voltage on the bit line is increased.
Conversely, if a logical data “0” is stored in the capacitor, the degree of polarization of the capacitor is varied from the point D to the point C, by the generation of a charge amount of dQ
0
, and returns to the point D. In this case, the voltage on the bit line is not changed. The bit line voltage is compared with a reference voltage by means of a sense amplifier circuit. If the bit line voltage is more than the reference voltage, it is increased up to an operational voltage level (i.e., V
cc
level) by a sense amplifier circuit. If not, the bit line voltage is lowered to zero voltage by the sense amplifier circuit.
However, as the degree of integration of the FRAM increases, the dimensions of each ferroelectric capacitor in a flat board structure decrease. Unlike a dynamic random access memory (DRAM) using a linear capacitor of a capacitor-on-bit line (COB) structure that is capable of increasing the dimensions of the capacitor, it may be very difficult to increase the dimensions of the ferroelectric capacitor using the present manufacturing technology. As a result of a reduction of the dimensions of the capacitor, a corresponding reduction occurs to a voltage V
b
induced on the bit line during the sensing operation. The voltage V
b
is expressed as follow.
V
b
=
Q
m
C
b
(
1
)
In equation (1), Q
m
indicates the amount of charge transmitted from the ferroelectric capacitor of the memory cell to the bit line coupled to the memory cell, and C
b
indicates a bit line capacitance. Q
m
is applied to both dQ
1
and dQ
0
.
The amount of charge Q
m
from the ferroelectric capacitor is decreased as the dimensions of the ferroelectric capacitor are reduced. Therefore, it can be seen from the equation that the bit line voltage V
b
, which is induced during the sensing operation, is reduced in proportion to the reduced amount of charge. As the bit line voltage V
b
is reduced, it can be easily changed through a capacitive coupling at voltage variations of adjacent signal lines (e.g., the bit lines, the word lines and the plate lines). This can in turn cause a malfunction of the sense amplifier circuit or of the FRAM itself.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a ferroelectric random access memory device capable of increasing a bit line voltage during a sensing operation and a read method thereof.
In order to attain the above object, according to an aspect of the present invention, a random access memory device is provided that comprises a top bit line, a top memory cell coupled to the top bit line, a bottom bit line corresponding to the top bit line, a sense amplifier coupled to the top and bottom bit lines, for sensing a voltage difference between the top and bottom bit lines, and a circuit for increasing a voltage of the top and bottom bit lines, before the sense amplifier is activated.
The circuit for increasing a voltage preferably comprises a first capacitor having a first electrode coupled to a first plate line, a first transistor having a first current path formed between the top bit line and a second electrode of the first capacitor, and a gate coupled to a first word line, a second capacitor having a first electrode coupled to a second plate line, and a second transistor having a current path formed between the bottom bit line and a second electrode of the second capacitor, and a gate coupled to a second word line.
The top memory cell preferably comprises a ferroelectric capacitor. The first and second capacitors preferably each comprise a capacitor selected from the group of a ferroelectric capacitor and a linear capacitor.
When the first and second capacitors comprise ferroelectric capacitors, a pulse signal is preferably applied simultaneously to the second electrodes of the first and second capacitors through corresponding first and second NMOS transistors after an inactivation of the first and second word lines, so that the first and second capacitors are polarized to an initial domain.
The first and second word lines are preferably activated simultaneously during a sensing operation. The first and second plate lines are preferably activated simultaneously during an activation of the first and secon
Jones Volentine, L.LC.
Mai Son
Samsung Electronics Co,. Ltd.
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