Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-10-24
2002-11-12
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S210130
Reexamination Certificate
active
06480410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device and method for driving the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1
shows an hysteresis loop of a related art ferroelectric memory device. As shown in
FIG. 1
, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described.
FIG. 2
shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in
FIG. 2
, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline W/L in the same direction as the wordline W/L, a transistor T with a gate connected with the wordline and a source connected with the bitline B/L, and a ferroelectric capacitor FC
1
. A first terminal of the ferroelectric capacitor FC
1
is connected with a drain of the transistor T and a second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described.
FIG. 3
a
is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and
FIG. 3
b
is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
In a period where the wordline is maintained at high state, a high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. If a low signal is applied to the bitline, and if the signal is applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor FC
1
.
With reference to
FIG. 3
b
, the reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from a high state to a low state, all the bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in the hysteresis loop of FIG.
1
. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in the case that the data is destroyed while the logic value “0” is output in the case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line P/L becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
The related art method for driving a nonvolatile ferroelectric memory device, as described above, has various disadvantages. When the data reading and writing operations are performed, it is necessary to activate the wordline from an active period of one cycle to a precharge period. In this case, it is difficult to restrict the quantity of charges generated from the cell. For this reason, it is difficult to uniformly write or read data in the whole cell array. In addition, since the sensing amplifier is activated when the wordline is activated at a high level, the capacitance difference between the main cell bitline and the reference cell bitline occurs. For this reason, the related art nonvolatile ferroelectric memory device has limitations in reducing the size of the cell by reducing the sensing voltage.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and method for driving the same that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and method for driving the same in which data reading and writing operations are performed uniformly in a whole cell array.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and method for driving the same in which the size of a cell is reduced by lowering a sensing voltage.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and method for driving the same in which writing and restoring operations are stably performed in even case of low voltage.
Another embodiment of the invention includes a nonvolatile ferroelectric memory device according to the present invention including a first sub cell array and a second sub cell array each including a plurality of main cells, each main cell of the plurality of main cells having a split wordline pair including a first split wordline and a second split wordline, a main bitline pair including a first bitline and a second bitline, the first bitline and second bitline formed across the split wordline and the second split wordline, a reference cell coupled to the first bitline and second bitline, and a first column selector between the first bitline and a data bus and a second column selector between the second bitline and the databus, the first and second column selectors for selectively selecting the first or second bitlines; and a first sensing amplifier and a second sensing amplifier connected between the first sub cell array and the second sub cell array.
To further achieve the above objects in whole or in part according to the present invent
Kang Hee Bok
Kim Duck Ju
Kye Hun Woo
Park Je Hoon
Birch & Stewart Kolasch & Birch, LLP
Dinh Son T.
Hynix / Semiconductor Inc.
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