Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1998-04-14
2001-07-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S154000, C365S158000
Reexamination Certificate
active
06269027
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the field of electronic memory devices, and more particularly, to non-volatile memory elements that assume a desired state when power is applied.
Most digital electronic devices use both logic gates and memory elements to implement a desired function. The memory elements are used to store initial, intermediate and/or final data. The logic gates are used to provide and/or receive the data to/from the memory elements, and perform the necessary data manipulation. In a typical digital system, the basic memory elements are bi-stable logic circuits known as latching elements. There are numerous types of latching elements including, for example, D-latches, RS-latches, JK-latches, etc. These latching elements are often combined to form various forms of flip-flops or other storage devices.
Latching elements typically use one or more feedback paths that have an even number of inversions. By providing an even number of inversions, the feedback path reinforces the data state of the latching element. To write a desired state to the latching element, the feedback path is typically overdriven or a switch is provided to temporarily interrupt the feedback path while a new data state is provided to the latching element. The most basic latching element includes a pair of cross-coupled inverters. There are, however, numerous other known implementations.
Conventional latching elements suffer from a number of limitations, some of which are described below. First, the initial state of a latching element is typically unknown. This limitation can cause a number of problems in a circuit or system. For example, the enable signal of selected output buffers is typically either directly or indirectly controlled by the state of a latching element. Because the state of the latching elements are unknown upon power-up, one or more of the output buffers may be enabled simultaneously. This is particularly problematic when the output buffers are coupled to a bidirectional bus where one buffer may attempt to overdrive another, thereby drawing significant power and possibly causing damage to selected circuit elements.
To alleviate this and other problems, many systems require an initialization procedure to be executed shortly after power-up. One purpose of the initialization procedure is to initialize the state of selected latching elements. The initialization procedure may, for example, reset selected latching elements to disable the output buffers of a circuit or system. Generally, the initialization procedure initializes selected latching elements to prepare the device for subsequent processing. Requiring an initialization procedure increases the time required to boot the system.
Another related limitation of many conventional latching elements is that the data stored therein is lost when power is lost or otherwise interrupted. For example, when a personal computer or other data processing system loses power, the data stored in the latching elements are lost. When power is restored, the data processing system assumes an initial state that is unrelated to the state of the data processing system before the power loss. Often, much of the processing that was completed coincident with or prior to the power loss is lost, or must be re-constructed and/or re-executed which can be a time consuming and tedious task.
In high reliability applications, a primary power source and an auxiliary power source may be provided to reduce the likelihood that the latching elements will experience a power loss. In such systems, an auxiliary power source is used when the primary power fails. A limitation of this approach is that significant overhead is required including an auxiliary power source, a power degradation detection mechanism and a power switching mechanism. In addition, the auxiliary power source is often a battery or the like that has a limited lifetime. Therefore, if the primary power source fails for an extended period of time, the auxiliary power source may also fail causing the latching elements to lose the data stored therein.
Another approach for minimizing the loss of data after a power failure is to maintain an audit trail for each transaction submitted to the system. In such a system, an audit trail is periodically written to a non-volatile storage medium such as a magnetic tape or hard drive. The audit trail typically includes a listing of the status of each transaction that is submitted to the processor. If the power fails, the latching elements within the system lose the data stored therein, as described above. However, after power is restored, the audit trail can be used to reconstruct that status of each transaction. Only those transactions that were not completed and stored must be re-submitted for processing. This can significantly reduce the amount of data reprocessing required after a power failure. However, significant time and resources are typically required to read the audit trail data and determined the status of each transaction.
It would be desirable, therefore, to provide a latching element that assumes a desired state upon power-up. This may reduce or eliminate the need for an initialization procedure. It would also be desirable to provide a latching element that does not lose data when power is lost or otherwise interrupted. This may reduce the need to provide an auxiliary power source and/or audit trail system or the like.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing a bi-stable latching element that assumes a known initial state upon power up. The present invention also provides a latching element that does not lose data when power is lost or otherwise interrupted. This is accomplished by incorporating one or more magnetic elements into the latching element. The magnetic elements preferably have at least two stable magneto-resistive states. By programming the magnetic elements to appropriate resistance values, the latching element may assume a desired or known initial state upon power up. By programming the magnetic elements each time the latching element is written during normal functional operation, the data stored therein may not be lost when power is lost or otherwise interrupted.
In one illustrative embodiment of the present invention, a latching element is powered by a power supply, and selectively stores a bit of data having one of two stable states. A first magnetic element is interposed between a first portion of the latching element and the power supply. The first magnetic element provides a first magnetically programmable resistance, which causes the latching element to assume a desired one of the two stable states upon power-up of the power supply. A second magnetic element may also be interposed between a second portion of the latching element and the power supply for providing a second magnetically programmable resistance, which may be different from the first magnetically programmed resistance. The second magnetic element may aid the latching element in assuming the desired one of the two stable states upon power-up of the power supply.
In another illustrative embodiment of the present invention, a latching element powered by a first voltage and a second voltage is provided. The latching element includes a first inverting logic element and a second inverting logic element coupled together in a cross-coupled configuration, wherein each of the first and second inverting logic elements has a first power supply terminal and a second power supply terminal. In this illustrative embodiment, a first magnetic element is provided between the first power supply terminal of the first inverting logic element and the first voltage. A second magnetic element is provided between the first power supply terminal of the second inverting logic element and the first voltage. The second power supply terminals of the first and second inverting logic elements are then coupled to the second voltage. Preferably, the first magnetic element is programmed to provide a different resistanc
Gadbois Jason B.
Hurst, Jr. Allan T.
Sather Jeff S.
Auduong Gene N.
Fredrick Kris T.
Honeywell Inc.
Nelms David
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