Non-volatile single-event upset tolerant latch circuit

Details Non-volatile single-event upset tolerant latch circuit Non-volatile single-event upset tolerant latch circuit

2011-06-21

2011-06-21

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S163000

Reexamination Certificate

active

07965541

ABSTRACT:
A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.

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