Non-volatile semiconductor memory device having storage cell arr

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257316, H01L 29788

Patent

active

058893059

ABSTRACT:
In a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit, the thickness of a gate oxide layer of the peripheral circuit area is independent of the formation of an O--N--O insulation layer on the storage cell area. A floating gate of a storage cell array is formed as a first conductive layer on a semiconductor substrate, an O--N--O insulation layer covering the floating gate is formed on the top surface of the substrate, and a gate oxide layer of the peripheral circuit area is formed by making an oxide layer on the top surface of the substrate after removing the O--N--O insulation layer on the top surface of the peripheral circuit area. The O--N--O insulation layer is solely formed on the top and side surfaces of the floating gate in the direction of word lines and absent from side surfaces of the floating gate in the direction of bit lines.

REFERENCES:
patent: 5063431 (1991-11-01), Ohshima
patent: 5149667 (1992-09-01), Choi
patent: 5150179 (1992-09-01), Gill
patent: 5158902 (1992-10-01), Hanada
patent: 5661330 (1997-08-01), Aimi et al.

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