Non-volatile semiconductor memory device and semiconductor...

Details Non-volatile semiconductor memory device and semiconductor... Non-volatile semiconductor memory device and semiconductor...

2007-10-23

2007-10-23

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189020, C365S191000, C365S230020, C365S230080

Reexamination Certificate

active

11194777

ABSTRACT:
For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

REFERENCES:
patent: 5668772 (1997-09-01), Hotta
Campardo, et al., “An Overview of Flash Architectural Developments,” Proceedings of the IEEE, Apr. 2003, pp. 523-536, vol. 91, No. 4.
Micheloni, et al., “The Flash Memory Read Path: Building Blocks and Critical Aspects,” Proceedings of the IEEE, Apr. 2003, pp. 537-553, vol. 91, No. 4.
Silvagni, et al., “An Overview of Logic Architectures Inside Flash Memory Devices,” Proceedings of the IEEE, Apr. 2003, pp. 559-580, vol. 91, No. 4.
Chimenton, et al., “Overerase Phenomena: An Insight Into Flash Memory Reliability,” Proceedings of the IEEE, Apr. 2003, pp. 617-625, vol. 91, No. 4.

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