Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-12
2003-12-23
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S589000, C438S593000
Reexamination Certificate
active
06667211
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrically programmable non-volatile semiconductor memory device having an electrode called a booster plate.
An EEPROM having an electrode called a booster plate is described, for example, in 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 238-239 (I. D. Choi, D. J. Kim, D. S. Jang, J. Kim, H. S. Kim, W. C. Shin, S. T. Ahn, and O. H. Kwon, Samsung Electronics Co., LTD.).
In this specification, the electrode called “booster plate” is referred to as “booster electrode.” An EEPROM cell having the booster electrode will now be generally described.
FIG. 1A
is a plan view of a conventional memory cell,
FIG. 1B
is a cross-sectional view taken along line B—B in
FIG. 1A
, and
FIG. 1C
is a cross-sectional view taken along line C—C in FIG.
1
A. For simple description, bit lines and an underlying interlayer insulating film are omitted in FIG.
1
A.
As is shown in
FIGS. 1A
to
1
C, device isolation insulation films
102
are formed in a surface portion of a P-type silicon substrate
101
. Device regions
103
are defined on a surface of the substrate
101
by the device isolation insulation films
102
.
A tunnel insulation film
104
, a floating gate
105
, an insulation film
106
and a word line
107
are successively formed on the device region
103
. A structure wherein the floating gate
105
and word line
107
are stacked is called a stacked-gate structure.
Reference numeral
108
denotes a gate of a select transistor. N-type diffusion layers
109
,
110
and
111
are formed in the device region
103
. The diffusion layer
109
is connected to a source line (not shown), and the diffusion layer
110
is to a bit line
112
. The number of diffusion layers
111
is two or more and these layers
111
function as source/drain regions of memory cell transistors, respectively.
A booster electrode insulating film
114
is formed over the periphery of the stacked-gate structure and the diffusion layers
111
. A booster electrode
115
is formed on the insulating film
114
. Reference numeral
144
denotes an interlayer insulation film.
FIG. 2A
shows an equivalent circuit of the conventional EEPROM. For the purpose of simple description,
FIG. 2A
shows the case where two word lines (WL
1
, WL
2
) and two bit lines (BL
1
, BL
2
) are provided.
As is shown in
FIG. 2A
, a select transistor ST
11
, cell transistors MC
11
and MC
21
and a select transistor ST
21
are connected in series between a bit line BL
1
and a source line SL.
Similarly, a select transistor ST
12
, cell transistors MC
12
and MC
22
and a select transistor ST
22
are connected in series between a bit line BL
2
and the source line SL.
A word line WL
1
is commonly connected to the gates of the cell transistors MC
11
and MC
12
, and a word line WL
2
is commonly connected to the gates of the cell transistors MC
21
and MC
22
.
A drain-side select gate line SG
1
is commonly connected to the gates of the select transistors ST
11
and ST
12
, and a source-side select gate line SG
2
is commonly connected to the gates of the select transistors ST
21
and ST
22
. A back-gate (BULK) of each transistor is common.
In the NAND type EEPROM, the potential of the back-gate BULK is varied in accordance with the operation mode. A booster electrode BP is capacitively coupled to the mutual connection nodes and floating gates FG
11
, FG
12
, FG
21
and FG
22
of the respective transistors.
The write operation will now be described on the basis of the disclosure in the above-mentioned document. In the following description, a write operation for injecting electrons into the floating gate is called “0” write, and a write operation for injecting no electrons into the floating gate is called “1” write.
FIG. 2B
shows potentials of respective nodes in the write mode.
In the NAND type flash EEPROM disclosed in the above-mentioned document, the potential of the selected word line WL
1
is set at 13V, the potential of the booster electrode BP is at 13V, the potential of the bit line BL
1
designated for “0” write is at 0V, the potential of the drain-side select gate line SG
1
is at 3.3V, the potential of the source-side select gate line SG
2
is at 0V, and the potential of the non-selected word line WL
2
is at 3.3V.
At this time, the potentials of both the write-selected word line WL
1
and booster electrode BP are 13V. A potential corresponding to about a coupling ratio (&ggr;pgm) “0.78” between the floating gate FG
11
and word line WL
1
can be produced at the floating gate FG
11
by a potential of the booster electrode BP, and a potential of about 10V is applied to the tunnel insulation film.
Accordingly, even if the write potential is 13V, electrons are injected into the floating gate FG
11
through the tunnel oxide film having about 10 nm thick. Thus, “0” write is effected in the cell MC
11
.
On the other hand, the gate potential of the cell MC
21
belonging to the same bit line BL
1
and having the gate connected to the non-selected word line WL
2
is 3.3V, and the potential of the booster electrode BP is 13V. At this time, the voltage of 3.3V applied to the word line WL
2
acts to lower the potential of the floating gate FG
21
. Thus, no electrons are injected in the floating gate FG
21
.
On the other hand, the potential of the bit line BL
2
designated for “1” write is 3.3V. Since the potential of the drain-side select gate line SG
1
is 3.3V at this time, the select transistor ST
12
is cut off when the potential of “3.3V-VthST” has been transferred to the N-type diffusion layer. As a result, the region
116
of the diffusion layer
111
shown in FIG.
1
B and channel
113
of the memory cell (hereinafter referred to as “NAND cell channel
116
” or simply “cell channel
116
”) is set in the floating state.
In this case, “VthST” is a threshold voltage of the select transistor ST
12
. At this time the potential of the cell channel
116
is raised by the potential of booster electrode BP.
The potential, 13V, of the selected word line WL
1
contributes to raising the potential of cell channel
116
through the floating gate FG
12
. In this manner the potential of cell channel
116
is raised up to about 8V.
In the cell MC
12
having the gate connected to the selected word line WL
1
, a potential difference between the channel thereof and the word line WL
1
decreases to “13V−8V=5V” and no electrons are injected in the floating gate FG
12
.
Thus, data “1” is written in the cell MC
12
. As described above, in the EEPROM having the booster electrode BP, the potential of the cell channel
116
is greatly raised up to about 8V in the write-selected cell MC
12
connected to the bit line BL
2
designated for “1” write.
In addition, in the cell MC
22
having the gate connected to the non-selected word line WL
2
, a potential difference between the channel thereof and the word line WL
2
is “3.3V−8V=−4.7V” and no electrons are injected in the floating gate FG
22
.
As has been described above, the main function of the booster electrode BP is to increase the effective coupling ratio &ggr;pgm so that the potential of the floating gate is sufficiently raised at the time of “0” write, thereby lowering the potential (write potential VPP) of the selected word line from 17V to 13V.
Furthermore, the channel potential of the cell for “1” write is raised from “3.3-VthST”, as in the prior art, to about 8V, thereby making it difficult for electrons to be injected in the floating gate. Thereby, occurrence of “erroneous write”, such as erroneous write of “0”, can be prevented.
However, in the conventional EEPROM having the booster electrode, the coupling ratio &ggr;pgm in write mode varies due to “processing error” at the time of forming the device isolation region
102
and “processing error” at the time of forming the floating gate
105
, as will be described below in detail.
FIG. 3
is a bird's eye view showing dimensions of the floating gate.
Suppose, as shown in
FIG. 3
, that the dimension of the floating gate
105
along t
Brophy Jamie L.
Hogan & Hartson LLP
Zarabian Amir
LandOfFree
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