Non-volatile semiconductor memory device and manufacturing...

Details Non-volatile semiconductor memory device and manufacturing... Non-volatile semiconductor memory device and manufacturing...

1999-04-06

2001-05-08

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S704000, C438S711000, C438S739000

Reexamination Certificate

active

06228712

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices employed in various computing devices, control equipment or the like, and a manufacturing method thereof.
2. Description of the Background Art
A non-volatile semiconductor memory device is used for writing/reading a piece of information, based on change in electric field effect to a channel portion caused by the electric charge in the floating gate, by applying a high voltage between a floating gate and a source or a drain, and injecting/pulling electric charge into/out from the floating gate. As the electric charge in the floating gate is isolated by an insulation film, it can be retained for a long time as non-volatile information even after the power-off.
A conventional non-volatile semiconductor memory device will be described with reference to FIG.
53
.
On a floating gate fin electrode
509
, a second gate insulation film
512
is formed and a control gate lower electrode
513
of polycrystalline silicon and a control gate upper electrode
514
of a metal silicide film are formed thereon. A control gate electrode
517
is formed of control gate lower electrode
513
and control gate upper electrode
514
. Further on control gate upper electrode
514
of the metal silicide film, a hard mask
515
which serves as a mask at etching is formed of a silicon oxide film.
Bit lines are arranged among sources/drains from the back to the front and word lines are arranged from the right to the left in the drawing.
In
FIG. 53
, control gate electrode
517
and second gate insulation film
512
in the front section are not shown to allow the viewer to see a central trench portion. A structure shown in
FIG. 53
is formed by etching control gate electrode
517
and second gate insulation film
512
using hard mask
515
of a silicon oxide film as a mask, removing a floating gate layer through anisotropic etching using control gate electrode
517
as a mask, and thereby forming a floating gate electrode
518
. Here, a polycrystalline silicon residue which is an etching residue
519
is left on a side wall of an insulation film facing the central trench portion.
Another example where etching residue remains is shown in
FIGS. 54 and 55
. An end portion itself of a floating gate electrode
618
serves as a mask at a step formed by an end of floating gate electrode
618
and an isolating insulation film
602
, and a polycrystalline silicon residue
619
is produced on a side wall of the step formed by isolating insulation film
602
and the end of the floating gate electrode as shown in FIG.
55
.
Generally, in a non-volatile semiconductor memory device such as a flash memory, capacitance coupling ratio C
2
/(C
1
+C
2
) must be high. Here, capacitance C
1
is capacitance between the floating gate electrode and a channel portion and capacitance C
2
is coupling capacitance between the control gate electrode and the floating gate electrode. When voltage V is applied from an external source to the control gate electrode, potential on the floating gate electrode is C
2
/(C
1
+C
2
). Therefore, in order to apply a sufficiently high voltage on the floating gate electrode, a correspondingly high capacitance coupling ratio is required. The high capacitance coupling ratio allows an operation of non-volatile semiconductor memory device at a low voltage while securing a high floating gate potential.
To increase the capacitance coupling ratio, capacitance C
2
between the control gate electrode and the floating gate electrode must be increased. Therefore, a fin electrode
509
is provided in an upper portion of the floating gate electrode thereby increasing the area between the floating gate electrode and the control gate electrode.
In the above described structure, some portions are undesirably masked from being etched at the anisotropic etching of floating gate electrode
518
of polycrystalline silicon or the like, and etching residue
519
tends to be produced along the side wall of the insulation film facing the trench portion. Such polycrystalline silicon residue forms short circuits between gate electrodes and as a result causes a significant yield reduction. In addition, even if etching selectivity between polycrystalline silicon and an underlying layer is made as high as possible to permit over-etching for the removal of the etching residue, there is a certain limitation in the etching selectivity and first gate insulation film
503
possibly be penetrated.
In addition, in non-volatile semiconductor memory devices such as a flash memory, for the increase in capacitance C
2
between the floating gate electrode and the control gate electrode which in turn increases the above mentioned capacitance coupling ratio, an area of the floating gate electrode, especially width thereof must be increased. Conventionally, the width of the floating gate electrode is increased by providing fin electrode
509
up to about three times the length of the channel portion. Therefore, the area of the floating gate electrodes is increased and hinders the miniaturization of non-volatile semiconductor memory devices.
SUMMARY OF THE INVENTION
An object of the present invention is to remove an etching residue or make the etching residue harmless without damaging a first gate insulation film and an interlayer insulation film. A further object of the present invention is to obtain a high capacitance coupling ratio without increasing an area of a floating gate electrode and to attain miniaturization of non-volatile semiconductor memory devices.
In one aspect of the present invention, a method of manufacturing includes the steps of: forming a first gate layer on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween; forming a second gate layer on the first gate layer with a second gate insulation film posed therebetween; forming a second gate electrode by etching the second gate layer using a resist as a mask; forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask; and performing an isotropic etching on an etching residue left on a side wall of a step formed by an insulation film in contact with a side wall of the first gate layer and the first gate insulation film, after the etching of the first gate layer, to remove the etching residue.
As the etching residue is removed by isotropic etching, short circuit between gate electrodes can be prevented and yield improvement can be achieved.
Preferably, a gas containing halogen element is employed in the above mentioned isotropic etching.
The etching residue can be removed without damages on the first gate insulation film and the interlayer insulation film through the use of gas containing halogen element, and yield improvement can be achieved.
In particular, the gas containing halogen element is preferably one of the following gases (1), (2) and (3).
(1) One selected from the group consisting of Cl
2
gas, a mixed gas of Cl
2
and NF
3
, a mixed gas of Cl
2
and O
2
, a mixed gas of Vapor HF and O
2
, a mixed gas of CF
4
and O
2
, a mixed gas of CHF
3
and O
2
, a mixed gas of SF
6
and O
2
, and a mixed gas of NF
3
and O
2
.
(2) A gas prepared by using one of N
2
O, CO
2
, O
3
, H
2
O
2
and H
2
O instead of O
2
in the gas of (1).
(3) A mixed gas prepared by further adding at least one of He, Ne, Ar, Kr, Xe and N
2
to the gas of (1).
In addition, a gas prepared by adding at least one of He, Ne, Ar, Kr, Xe and N
2
to the gas of (2) can be employed.
With the use of these gases, the etching residue can be efficiently removed without damages on the first gate insulation film and the interlayer insulation film. As a result, short circuit between gates can be prevented and yield improvement is allowed.
When formation of a non-uniformly etched side wall of the second gate electrode is not desired at the above mentioned isotropic etching, a step of forming a protective film on the side wall of the second gate electrode desirably is further included pr

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