Non-volatile semiconductor memory device and its...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S201000, C438S211000, C438S275000

Reexamination Certificate

active

07005345

ABSTRACT:
In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

REFERENCES:
patent: 4766088 (1988-08-01), Kono et al.
patent: 5036018 (1991-07-01), Mazzali
patent: 5600164 (1997-02-01), Ajika et al.
patent: 5824583 (1998-10-01), Asano et al.
patent: 5841174 (1998-11-01), Arai
patent: 5852311 (1998-12-01), Kwon et al.
patent: 5913120 (1999-06-01), Cappelletti
patent: 5989957 (1999-11-01), Ngo et al.
patent: 62-23149 (1985-07-01), None
patent: 62-76668 (1985-09-01), None
patent: 62-045165 (1987-02-01), None
patent: 02-246376 (1990-10-01), None
patent: 05-183134 (1993-07-01), None
patent: 05-190811 (1993-07-01), None
patent: 7-297304 (1995-03-01), None
patent: 08-23041 (1996-01-01), None
Hannon, et al., “0.25 μm Merged Bulk DRAM and SOI Logic Using Patterned SOI”, 2000 Symposium on VLSI Technology Digest of Technical Papers pp., 66-67.
Scheuerlein, et al., “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC 2000/Session 7/TD: Emerging Memory & Device Techmologies/Paper TA 7.2, pp. 128-129.
Yamada, et al., “An Embedded DRAM Technology on SOI/Bulk Hybrid Substrate Formed with SEG Process for High-End SOC Application”, 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 112-113.
Hannon, et al., “0.25 μm Merged Bulk DRAM and SOI Logic Using Patterned SOI”, 2000 Symposium on VLSI Technology Digest of Technical Papers pp., 66-67.
Wolf, et al. “Silicon Processing for the VLSI Era,” 1986, Lattice Press, vol. 1, pp. 384-388.

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