Non-volatile semiconductor memory device and a method of...

Details Non-volatile semiconductor memory device and a method of... Non-volatile semiconductor memory device and a method of...

2005-02-22

2005-02-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S266000, C438S289000, C438S591000, C438S595000, C257S298000, C257S314000, C257S316000, C257S908000

Reexamination Certificate

active

06858497

ABSTRACT:
The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1and BL2) formed on two impurity regions S/D, two first control electrodes CG1and CG2formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1and CG2in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1and CG2become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.

REFERENCES:
patent: 5654568 (1997-08-01), Nakao
patent: 6069382 (2000-05-01), Rahim
patent: 62-291970 (1908-12-01), None
patent: 5-190863 (2001-06-01), None
patent: 2001-156188 (2001-06-01), None
“Twin MONOS Cell With Dual Control Gates”, Hayashi, Y. et al.; 2000 Symposium on VLSI Technology Digest of Technical Papers, Jun. 2000; pp. 122-123.

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