Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1999-06-22

2002-02-12

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S258000, C438S262000

Reexamination Certificate

active

06346443

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor devices. In particular, the present invention relates to non-volatile semiconductor memory devices such as electrically erasable and programmable read-only memory (EEPROM) devices and flash EEPROM devices.
BACKGROUND OF THE INVENTION
An electrically erasable and programmable read-only memory (EEPROM) device typically comprises an array of M×N floating gate cells that may be individually addressed in order to be programmed, read or erased. As shown in
FIG. 1
, each cell typically comprises a source S and a drain D, e.g. n-type regions, formed in a semiconductor substrate
2
, e.g. a p-type substrate. A channel CH is disposed between the source S and the drain D. Each cell further comprises a gate structure which is commonly formed of a floating gate FG overlying the channel CH, and a control gate CG overlying the floating gate FG. The floating gate FG is separated from the surface of the semiconductor substrate
2
by a first thin dielectric layer
4
, also referred as the “tunnel oxide”, and is isolated from the control gate CG by a second dielectric layer
6
.
As shown in the schematic diagram of
FIG. 2
, the individual memory cells forming the array are organized into rows and columns. Individual word lines WL (WL/
1
to WL/M) form control gate CG of each cell within a row, and respective bit lines BL (BL/
1
to BL/N) electrically connect the drain D of each cell within a column. Each cell within a column further shares source S and drain D with adjacent cells. By activating the corresponding word WL and bit BL lines, each cell may thus be individually addressed in order to be programmed or read. The source S of each cell within the array may be connected to a common source line CS as illustrated in FIG.
2
. This particular feature allows the erasure of every memory cells within the array simultaneously, i.e. in one “flash” operation. The memory device which is illustrated in
FIG. 2
is therefore known as a flash EEPROM. Alternatively, the source S of each cell within a column may be connected to additional bit lines as in conventional EEPROM devices.
Each cell may be charged or discharged, i.e. programmed or erased, by appropriately injecting electrons into or withdrawing electrons from the floating gate FG. Charging and discharging of the floating gate FG occurs by tunnelling effects through the first thin dielectric layer
4
. Charging the floating gate FG will generally raise the threshold voltage VT of the cell, thus also the voltage VG that must be applied to the control gate CG in order to create a conductive path between source S and drain D. Thus, by applying a voltage to the control gate CG which is greater than the threshold voltage of a discharged cell but lower than the threshold voltage of a charged cell, the state of the cell can be determined by sensing the current flowing between drain D and source S of the memory cell. Accordingly, an unprogrammed cell will conduct, representing the logic state “zero”, whereas a programmed cell will not conduct, representing the logic state “one”.
The performance of the cell, i.e. the ability to perform programming and erasing operation, is essentially related to the capacitive coupling existing between control gate CG and floating gate FG. Maximizing this capacitive coupling will facilitate programming and erasing of the cell. This implies increasing the capacitance between the floating gate FG and the control gate CG. One will thus seek to increase the surface area between the floating gate FG and the control gate CG. However one will also wish to reduce the surface area of the memory device in order to increase the density of the device and reduce the costs of manufacture. In order to achieve both of these contradictory objectives, there is known from the prior art to form a memory cell in a trench structure. For instance, U.S. Pat. No. 4,979,004 discloses a method of forming an electrically programmable read-only memory (EPROM) device comprising a plurality of trenched memory cells. The capacitive coupling between the floating gate and the control gate is increased whereas the surface area is kept minimal because the two gates overlap each other vertically in the trench.
The method disclosed in this patent can be applied to form electrically erasable and programmable read-only memory (EEPROM) devices but has however some drawbacks. In particular, prior to the etching processes which are ultimately performed in order to form the individual cells, the first dielectric layer and the first conductive layer of each cell within a column therefore form a continuous lining along the trench interior. After the formation of the second dielectric layer and the second conductive layer, an anisotropic etching process is thus performed in order to form the respective gate structures and word lines. Consequently, in order to separate each memory cell within a trench, i.e. within a column, the etching process has to be performed until the first dielectric layer lying at the bottom of the trench is reached. Despite the use of highly anisotropic etching processes, defects will be induced in the dielectric layers eventually causing current leakage problems between the control gate and the floating gate and between the floating gate and the substrate, thus impairing the performance and data endurance of the memory device. In the case of EEPROM devices, it is more than likely that these problems will appear as the first dielectric layer, i.e. the tunnel oxide, is very thin so that the tunnelling effect can occur.
SUMMARY OF THE INVENTION
Thus, the present invention has as a purpose to overcome the inconveniences of the prior art and to provide a method of forming an EEPROM device which has improved performances and reduced surface area.
The present invention also has as a purpose to provide a method of forming an EEPROM device which is more reliable than that known from the prior art.
To this effect, the present invention has as object a method of forming a non-volatile memory device according to claim
1
.
An advantage of the present invention lies in the fact that the surface area of the memory device is substantially reduced. Indeed, due to the fact that each memory cell is formed in a well, the whole surface of the memory device is reduced.
Another advantage of the present invention lies in the fact that the costs of manufacture of the semiconductor device are reduced.
Another advantage of the present invention lies in the fact that the capacitive coupling between the floating gate and the control gate of the memory cells is improved. Indeed, the control gate overlaps the floating gate along the sidewalls of the well, thereby increasing the capacitance between the two gates. Accordingly, the performances of the memory device are improved.
Still another advantage of the present invention lies in the fact that the memory cells are more reliable than those of the prior art because they are formed in wells rather than trenches. The drawbacks of the prior art method are thus avoided.


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S. Wolf, “Silicon Processing for the VLSI Era: vol. 2—Process Integration”, Lattice Press, 1990 pp. 45-48.

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