Non-volatile semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365185, 365196, G11C 1606

Patent

active

054084326

ABSTRACT:
A non-volatile semiconductor memory device includes a sense amplifier (6) for detecting and outputting data of a memory cell comprising a non-volatile transistor (MO1, MO2), latch circuit (20) responsive to a latch signal for latching an output of the sense amplifier and inhibition means (10) responsive to a latch inhibition signal for inhibiting a latching operation of the latch circuit. With this construction of the memory device, correct data in the memory cell can be read without influence of noise in a circuit portion by detecting a verify mode automatically and monitoring a variation of a signal DO without using the latch circuit.

REFERENCES:
patent: 4575824 (1986-03-01), Tanaka et al.
patent: 4707809 (1987-11-01), Ando
patent: 5051955 (1991-09-01), Kobayashi
patent: 5146427 (1992-09-01), Sasaki et al.

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