Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1990-06-21
1994-06-21
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
365185, H01L 2968
Patent
active
053230396
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data.
BACKGROUND ART
A ROM, the storage contents of memory cells of which can be electrically erased and changed, is known as an EEPROM (electrically erasable programmable ROM). When compared with an EPROM, EEPROM can be used more easily since data are erased with electric signals while being mounted on a circuit board, since the demands for use with various control circuits, memory cards or the like are rapidly increasing. A large scale EEPROM in particular which is used when changing data in a floppy disk has been recently desired.
FIGS. 1A to 1C show the structure of the memory array of a conventional NAND type EEPROM suitable for large scale integration. FIG. 1A is a plane view of the pattern, FIG. 1B is a cross section along line A--A' of FIG. 1A, and FIG. 1C is a cross section along line B--B' of FIG. 1A. Referring to FIG. 1A, a portion enclosed by a broken line and indicated at 10 represents one NAND basic block. As understood from FIG. 1B, this NAND basic block 10 is partitioned from other NAND basic blocks disposed in the right/left direction as viewed in FIG. 1B by field oxide films 12, 12, . . . . The vertical cross section of the NAND basic block 10 is as shown in FIG. 1C. Specifically, referring to FIG. 1C in particular, reference numeral 11 represents a p-type silicon semiconductor substrate, 13 a common source region made of an n.sup.+ diffusion layer and shared by respective basic blocks 10, 14 a drain region of the NAND basic block 10 which region is also made of an n.sup.+ diffusion layer, 15, 15, . . . source/drain regions of memory cells within the NAND basic block 10 which regions are made of n.sup.+ diffusion layers, 16, 16, . . . floating gates made of a first polysilicon layer, 17, 17, . . . control gates made of a second polysilicon layer, 18 a first select gate constructed by electrically connecting together the first and second polysilicon layers, 19 a second select gate constructed by electrically connecting together the first and second polysilicon layers, 20 a data line, 21 a contact connecting the drain region 14 and the data line 20, 22 a gate oxide film formed between the floating gate 16 and the substrate 11 and having a thickness of, e.g., about 100 .ANG., 23 a gate insulating film formed between the floating gate 16 and the control gate 17 for which the film has a thickness of about 300 .ANG. and a three-layered structure of, e.g., ONO (oxide-nitride-oxide), 24 an insulating oxide film, and 25 and 26 gate oxide films formed between the substrate 11 and the first and second select gates 18 and 19, respectively, and having a thickness of, e.g., about 400 .ANG.. This gate oxide film 25 may be of the ONO three-layered structure which is formed at the time of forming the gate oxide film 23. In this case, the select gate transistors 18 and 19 are made of only the second polysilicon layer without using the first polysilicon layer. As seen from FIG. 1C in particular, each NAND basic block 10 is formed with ten transistors (memory cells and select gate transistors) 31 to 40 which will be described later in detail. The transistors 31 to 40 are turned on and off by means of gates 17 to 19 of respective channels. The on/off of the transistors 32 to 39, however, is controlled in dependence upon whether each floating gate 16 has electrons or holes.
Each floating gate 16 stores "1" or "0" in dependence on whether it has electrons or holes.
The number of control gates 17, 17, . . . provided for each NAND basic block 10 is, for example, eight. Each control gate is formed continuously to cover a plurality of floating gates 16, 16, . . . positioned under the control gate. Namely, as seen from FIGS. 1A and 1B in particular, the width (width in the up/down direction as viewed in FIG. 1A) of each floating gate 16, 16, . . . is the same as that of each control gate 17, 17, . . . , and the length (length in the right/left direction
REFERENCES:
patent: 4962481 (1990-10-01), Choi et al.
patent: 5017980 (1991-05-01), Gill et al.
Y. Itoh, et al., "An Experimental 4Mb CMOS EEPROM with a NAND structured Cell," ISSCC89, 10.4, Feb. 1989, pp. 134-135.
M. Momodomi et al., "New Device Technologies for 5V-Only 4Mb EEPROM with NAND structure Cell," IEDM 88, 17.1, Dec. 1988, pp. 412-415.
R. Shirota et al., "A New Cell for Ultra High Density 5V-Only EEPROMs," VLSI Technology Digest of Technical Papers, May, 1988, pp. 33-34.
R. Stewart et al., "A High Density EPROM Cell and Array", Symposium on VLSI Technology Digest of Technical Papers; May 1986, pp. 89-90.
M. Momodomi et al., "A High Density NANS EEPROM with Block-Page Programming for Microcomputer Applications," May, 1989; CICC89, pp. 10.1.1-10.1.4.
Asano Masamichi
Endoh Tetsuo
Inoue Satoshi
Iwahashi Hiroshi
Kirisawa Ryouhei
Crane Sara W.
Kabushiki Kaisha Toshiba
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