Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-07
2002-10-08
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000
Reexamination Certificate
active
06461916
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor device and also to a method for fabricating that semiconductor device; and, more particularly, the invention relates to a technique which is effective when applied to fineness and mass storage of a non-volatile semiconductor memory.
BACKGROUND OF THE INVENTION
There is an electrically rewritable non-volatile semiconductor storage known as a so-called AND-type flash memory, which is set out, for example, in Japanese Laid-open Patent Application No Hei 07-273231. In that publication, the following fabrication method is described as a technique for improving the degree of integration of transistors, called memory cells, existing in a chip.
More particularly, a three-layered built-up film, consisting of a gate oxide film, a first polysilicon layer and a silicon nitride film,is deposited on a semiconductor substrate made of single crystal silicon, and this is followed by patterning the built-up film in the form of stripes. Next, n-type impurity ions are implanted into the semiconductor substrate at portions which have not been covered with the patterned built-up film to form column lines of an n-type impurity semiconductor region in the surface of the semiconductor substrate. Thereafter, after deposition of an oxide film by CVD (Chemical Vapor Deposition), the silicon oxide film formed by the CVD method is etched by anisotropic dry etching to form a side wall spacer on the side walls of the first polysilicon layer and silicon nitride film. Using the first polysilicon layer and the side wall spacers as a mask, grooves are formed in the semiconductor substrate by anisotropic dry etching. In this manner, the n-type impurity semiconductor region is isolated, thereby forming column lines and source lines, respectively. Next, after formation of a silicon oxide film on the surface of the grooves, a second polysilicon layer is attached (deposited) over the entire surface of the semiconductor substrate, and this is followed by etching back the second polysilicon layer by isotropic dry etching until the silicon nitride film is exposed. The surface of the etched-back second polysilicon layer is oxidized to form an element isolation region made of the polysilicon covered with the silicon oxide film. Subsequently, the silicon nitride film is removed, and a third polysilicon layer is further attached and subjected to patterning so as to protect the first polysilicon layer therewith, thereby forming floating gates in parallel with the column lines. Thereafter, an interlayer insulating film and a fourth polysilicon layer are attached, and this is followed by patterning to form column lines made of the fourth polysilicon layer and disposed so as to be vertical to the column lines. Eventually, the first and third polysilicon layers are mutually isolated from each other to form floating gates.
In the AND-type flash memory formed in this way, electrons are stored in the floating gate to constitute a semiconductor device having a non-volatile memory function. Especially, the n-type impurity semiconductor region, which is formed with the first polysilicon layer at opposite sides thereof, serves as a source or drain region. In the method set out above, the processing of the first polysilicon layer and the formation of the element isolation region are performed by use of a one-layer mask pattern, so that no alignment allowance for the gate and the element isolation region is necessary, thereby enabling one to reduce a cell area.
In Japanese Laid-open Patent Application No. Hei 06-77437, there is described a technique concerning a working system of a non-volatile semiconductor memory. In the non-volatile- semiconductor memory set forth in that publication, when electrons are released from a floating gate to write data in a memory cell, a negative voltage is applied to a control gate electrode, while a positive voltage or zero voltage is applied to a drain terminal, thereby describing a technique for selective writing of the data.
Moreover, in Japanese Laid-open Patent Application No. Hei 08-107158, there is described a technique concerning high-speed reading and writing of a non-volatile semiconductor memory. The non-volatile semiconductor memory set out in that publication is fabricated by forming an element isolation region according to the LOCOS (Local Oxidation Of Silicon) method, by forming a first floating gate electrode (lower layer), and source and drain regions, covering the first floating gate electrode with an interlayer insulating film, removing the insulating film by an etching-back method or the CMP (Chemical Mechanical Polishing) method, and forming a second floating gate electrode (upper layer) on the first floating gate electrode.
In Japanese Laid-open Patent Application No. Hei 08-148658, there is described a technique concerning a fabrication method suited for a high degree of integration of a non-volatile semiconductor memory. The non-volatile semiconductor memory set out in that publication is fabricated by patterning a polysilicon layer for floating gates, and forming a polysilicon layer for use as gate electrodes of a peripheral circuit and an insulating film so as to permit them to run on the patterned layer.
SUMMARY OF THE INVENTION
However, we have found that the above-stated techniques present the following problems.
1. In the operation of electron withdrawal using the drain terminal, it is necessary to overlap the drain region and the floating gate. Accordingly, the gate length of the memory cell could not be shortened, making it difficult to achieve an intended cell fineness.
2. As a procedure for establishing isolation of memory cells, thermal oxidation is used, so that an excess thermal treating step was added after the formation of a gate oxide film, which made it difficult to ensure the reliability of the gate oxide film. Moreover, it was also difficult to suppress the elongation of the impurity semiconductor region caused during the thermal treating step.
3. A grooved structure is used as a method of forming an isolation region of the memory cells. The polysilicon layer is used as a burying material, so that a difficulty arose concerning the high withstand voltage isolation between the cells.
4. In non-volatile semiconductor memories, such as the AND-type memory flash memories proposed in the above-described techniques, no method of forming memory cells and MOS transistors serving as peripheral circuits and arranged on the same semiconductor substrate is disclosed at all. The fineness of memory cells proceeds through the development of processing techniques. However, a high voltage is used for write and erase operations, and thus, transistors for peripheral circuits are required to have such a specification as to withstand high voltages. For instance, in the fabrication method wherein an impurity semiconductor region of an MOS (Metal-Oxide-Semiconductor) transistor of a peripheral circuit is formed after formation of memory cells, it is difficult to form, on the same substrate, memory cells which should be a shallow junction impurity semiconductor region and the MOS transistor of the peripheral circuit which should have a deep junction structure. More particularly, the impurity semiconductor region of the memory cell should have a shallow junction so as to prevent punch through. On the other hand, the impurity semiconductor region of the high withstand voltage MOS transistor existing in a peripheral circuit permits field relaxation at the junction portion through an annealing step in order to ensure a high withstand voltage. After the formation of the memory cells, if a transistor of the peripheral circuit is formed, an additional annealing step is added to formation of the memory cells. As a result, the punch through resistance is lowered, making it impossible to assure the operation of the transistor having a short gate length.
5. In non-volatile semiconductor memories,such as AND-type flash memories, an MOS transistor for memory cell selection is arranged in a memory mat, but its formation method is not describe
Adachi Tetsuo
Kato Masataka
Kobayashi Takashi
Matsuzaki Nozomu
Mine Toshiyuki
Antonelli Terry Stout & Kraus LLP
Elms Richard
Hitachi , Ltd.
Owens Beth E.
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