Static information storage and retrieval – Read/write circuit – Testing
Patent
1990-07-17
1991-11-12
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Testing
365185, 36518905, 371 214, 324158T, G11C 2900
Patent
active
050653660
ABSTRACT:
A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.
REFERENCES:
patent: 4802166 (1989-01-01), Casagrande et al.
patent: 4833646 (1989-05-01), Turner
patent: 4967415 (1990-10-01), Tanagawa
patent: 4972144 (1990-11-01), Lyon et al.
Bennett Daniel H.
Dodd Gary L.
Murray Kenelm G. D.
Clawson Jr. Joseph E.
Denson-Low W. K.
Gudmestad Terje
Hughes Microelectronics Limited
Walder Jeannette M.
LandOfFree
Non-volatile RAM bit cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile RAM bit cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile RAM bit cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1017717