Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-02-28
2009-12-29
Chace, Christian P (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C711S150000, C365S218000, C365S185290, C365S185300
Reexamination Certificate
active
07640389
ABSTRACT:
A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.
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Choy Jon S.
Eguchi Richard K.
Chace Christian P
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Hill Daniel D.
Thammavong Prasith
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