Non-volatile memory device with enlarged trapping layer

Details Non-volatile memory device with enlarged trapping layer Non-volatile memory device with enlarged trapping layer

2002-05-13

2004-03-30

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S954000

Reexamination Certificate

active

06713332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to non-volatile memory devices having two bits per cell.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of provided power. The read-only memory (ROM) is a non-volatile memory device commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices are conventionally arranged into a plurality of memory cell arrays. Each memory cell includes a transistor, which typically comprises a metal-oxide-semiconductor field effect transistor (MOSFETs) that is juxtaposed between two intersecting bit lines and a word line. Data bit values or codes held by these memory cell transistors are permanently stored (until deliberate erasure) in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
A relatively recent development in non volatile memory has been the advent of Nitride-Read Only Memory (NROM) devices. NROM devices offer a number of advantages over the 30 year old currently dominant floating gate devices such as EPROM, Flash, and EEPROM, which store charge in a conductive floating gate.
NROM cells can comprise 2 bit flash cells based on charge storage in an Oxide-Nitride-Oxide (ONO) dielectric. The NROM cell may comprise an n-channel MOSFET device wherein nitride is used as a trapping material between a top and bottom oxide. The ONO structure replaces the gate dielectric that is used in floating gate devices. The top and bottom oxide layers should be thicker than 50 A to prevent any oxide damaging direct electron tunneling during programming.
NROM flash blocks may be added to standard CMOS processes by laying down the ONO layer after the field isolation but before the gate oxidation. Adding the NROM components typically has minimal effects on the CMOS thermal budgets. The NROM memory cells can be programmed by channel hot electron (CHE) injection, and erased by tunneling enhanced hot hole (TEHH) injection through the bottom oxide. The NROM cells operate as localized charge storage devices, which allows the trapped charge to remain only at the injection point. Thus, single bit failures commonly experienced by floating gate technologies may be reduced. This reduction may allow for further minimization of device size and increased device density without degradation in performance.
NROM devices can offer a number of significant advantages over floating gate devices. Both the bit size and the die size can be a factor of 3 or more smaller for NROM devices. NROM devices can also require 6 to 8 fewer photomask steps, their process complexity can be simpler, and it can be easier to integrate them with CMOS devices for embedded applications. Furthermore, NROM devices can be more suited to low voltage product implementation due to a lower erased threshold voltage. However, a common problem with NROM devices can be the lateral leakage of trapped charge over the ONO layer edge. Another problem that may occur with manufacturing memory devices having critical dimensions (CD) below around 0.15 &mgr;m, is a failure to properly resolve the device geometries when undergoing photolithographic processing.
SUMMARY OF THE INVENTION
The present invention relates to nonvolatile memory devices and methods of forming such nonvolatile memory devices. More particularly the invention herein provides improved methods of manufacturing NROM memory devices. The improved processing methods may reduce the occurrence of electron leakage from the trapped charge in the nitride layer during high stress operation conditions such as high voltage and/or high temperature. Such leakage may occur at the ONO layer edge. However, forming an ONO stack that has a larger area than the gate structure (i.e., the portion of a word line between two bit lines) and which overlaps the adjoining bit lines in accordance with the present invention, can attenuate or eliminate this problem. The invention also provides a dielectric resolution enhancement coating technique to overcome photolithography limitations of patterning the ONO stack below dimensions around 0.15 &mgr;m. Using a dielectric resolution enhancement coating technique in accordance with the present invention can allow for device dimensions which are smaller than the wavelength of the UV radiation used to pattern the photoresist and create the devices.
In accordance with an aspect of the present invention, a method for forming at least one nonvolatile memory device can comprise the steps of: (a) forming a trapping layer on a prepared semiconductor substrate; (b) forming a patterned photoresist layer on the trapping layer; (c) using the photoresist layer as an implanting mask to perform an implantation to form at least one bit line; (d) forming a first polymer layer on surfaces of the photoresist layer; (e) using the first polymer layer as an etching mask to pattern the trapping layer into at least one trapping layer strip; (f) removing the first polymer and the photoresist layer; (g) forming an oxide beside the at least one trapping layer strip and above the at least one bit line; (h) forming at least one word line on the at least one trapping layer strip; (h) forming a second polymer layer on surfaces of the at least one word line; (i) using the second polymer layer as an etching mask to pattern the at least one trapping layer strip into a plurality of trapping layer blocks; and (j) removing the second polymer.
The trapping layer may comprise in sequence a first oxide layer, a nitride layer, and a second oxide layer, wherein the first oxide layer, nitride layer, and second oxide layer form an ONO stack. The ONO stack may be patterned such that the first oxide layer remains substantially unpatterned. A BARC may be deposited prior to the application of the photoresist layer. The at least one bit line may comprise a plurality of bit lines, the at least one trapping layer strip may comprise a plurality of trapping layer strips, and the at least one word line may comprise a plurality of word lines.
In accordance with another aspect of the present invention, a method for forming a nonvolatile memory on a semiconductor substrate can comprise the steps of (a) providing a prepared semiconductor substrate; (b) forming a trapping layer on the semiconductor substrate; (c) applying and patterning a photoresist over the trapping layer to form a plurality of photoresist strips; (d) selectively implanting the semiconductor substrate to form a plurality of bit lines; (e) forming a first polymer on the surfaces of the patterned photoresist; (f) forming a plurality of trapping layer strips by etching back portions of the trapping layer; (g) removing the first polymer and the patterned photoresist; (h) forming an oxide over the plurality of bit lines; (i) forming a plurality of word lines; (j) forming a second polymer over the word lines; (k) etching portions of the plurality of trapping layer strips to form a plurality of trapping layer block structures; and (l) removing the second polymer.
The trapping layer may comprise in sequence a first oxide layer, a nitride layer, and a second oxide layer, the first oxide layer, nitride layer, and second oxide layer forming an ONO stack. The second oxide layer formed in the foregoing method may consume some portion of the nitride layer during its growth. The etch performed in step (f) may remove portions of the second oxide layer and the nitride layer, and may remove a relatively small portion of the first oxide layer. The first polymer and second polymer can be formed using a dielectric resolution enhancement coating technique, which may be performed in an etcher. The first polymer and second polymer may be used as etch masks to protect the underlying layers during etch processing. The word l

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