Non-volatile memory device with a charge trapping layer

Details Non-volatile memory device with a charge trapping layer Non-volatile memory device with a charge trapping layer

2008-12-30

2011-10-25

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S326000, C257SE29309

Reexamination Certificate

active

08044453

ABSTRACT:
A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

REFERENCES:
patent: 7692236 (2010-04-01), Brennan et al.
patent: 2006/0208302 (2006-09-01), Shin et al.
patent: 2007/0126054 (2007-06-01), Jung
patent: 2007/0155124 (2007-07-01), Ahn et al.
patent: 2009/0053871 (2009-02-01), Ahn
patent: 2000-286349 (2000-10-01), None
patent: 10-0643468 (2006-10-01), None
patent: 10-0643542 (2006-11-01), None

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