Non-volatile memory device having dual gate

Details Non-volatile memory device having dual gate Non-volatile memory device having dual gate

2007-08-21

2007-08-21

Landau, Matthew C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257SE29309

Reexamination Certificate

active

10726911

ABSTRACT:
A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate pattern. A gate insulation pattern is interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern. A cell channel region includes a first channel region defined in the semiconductor substrate under the selection gate electrode and a second channel region defined in the semiconductor substrate under the control gate electrode.

REFERENCES:
patent: 5349222 (1994-09-01), Shimoji
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6784476 (2004-08-01), Kim et al.
patent: 6785165 (2004-08-01), Kawahara et al.
patent: 2002/0145160 (2002-10-01), Lung

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