Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-20
2003-07-15
Chaudhan, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S664000
Reexamination Certificate
active
06593188
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2001-11134, filed on Mar. 5, 2001, the contents of which are herein-incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and fabrication methods thereof and, more particularly, to non-volatile semiconductor memory devices having a silicide layer and fabrication methods thereof.
BACKGROUND OF THE INVENTION
Generally, a flash memory device retains information stored in its memory cells even when no power is supplied. These days, the flash memory device is widely used in various kinds of electronics products such as a mobile telecommunication system, a memory card and so on.
The flash memory device generally comprises a cell array area and a peripheral area. The cell array area comprises a plurality of memory cells organized in a two-dimensional matrix. The peripheral area is generally formed to surround the cell array area. In the peripheral area, there is circuitry for performing a programming operation, a reading operation, an erasure operation and so on. A stacked gate cell is used as a unit cell of a number of flash memory devices with an advantage of its small cell size (surface area). The stacked gate cell has a floating gate electrode and a control gate electrode. Typically, the control gate electrode is stacked on the floating gate electrode.
Recently, an operation speed characteristic is considered important in high-density flash memory devices. For the higher operation speed, it is required to decrease signal delay time, which is induced by high resistance of gate electrodes in a peripheral area and control gate electrodes, i.e. word lines in a cell array area. In general, as an approach to reduce resistance of gate electrodes of MOS transistors, polycide technology has been used in industry. But, there are some problems in applying the polycide technology to flash memory devices, especially where a stacked gate cell is used therein.
One example of the polycide gate electrode technology is disclosed in U.S. Pat. No. 5,869,396 to Pan et al. According to the patent, an insulating layer is formed on a whole surface of a semiconductor substrate having polysilicon patterns. The insulating layer is planarized to expose an upper surface of the polysilicon patterns. A metal suicide layer of low resistance is selectively formed on the exposed upper surface.
As mentioned above, the patented technology is not applicable to fabricating the non-volatile memory devices such as flash memory devices, for following reason. Generally, a flash memory device has both a cell transistor and a select transistor. The select transistor has a single gate structure being different from the cell transistor, which has a stacked gate structure. That means the height of the select transistor is significantly lower than of the cell transistor. In this configuration, it is very difficult by using the patented method to expose both the surface of a gate electrode of the select transistor (i.e. a select line) and the surface of a control gate electrode of the cell transistor simultaneously. That is to say, the surface of the select line is still not exposed, though a planarization process is performed to the extent that the surface of a control gate electrode is exposed.
U.S. Pat. Nos. 5,731,239, 5,334,545, 5,447,875 and 6,107,096, describe methods for selectively forming a metal silicide layer on gate electrodes and/or source/drain regions of MOS transistors having only the single gate structure. These technologies are not applicable also to fabricating the non-volatile memory devices having both the single gate structure and the stacked gate structure on single substrate. The technologies cannot avoid the problems induced by structurally unique aspects of the non-volatile devices including the height difference of the single gate structure and the stacked gate structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a non-volatile memory device, which has metal silicide layers of low resistance on a select line and a control gate electrode.
It is an object of the present invention to provide a non-volatile memory device having enhanced operation characteristics, which has metal silicide layers of low resistance on a select line and a control gate electrode.
According to one aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises forming a first layer on a substrate. An intervening layer is formed on the first layer. A second layer is formed on the intervening layer. A capping layer is formed on the second layer. A first opening is formed to expose a portion of the first layer. The first opening penetrates the capping layer, the second layer and the intervening layer. A second opening is formed to expose a portion of the second layer. The second opening penetrates the capping layer. A reactive layer is formed on the exposed portion of the first layer, on the exposed portion of the second layer and on the capping layer. The reactive layer is reacted with the exposed portion of the first layer and the exposed portion of the second layer. As a result, a first top layer of a first crystalline structure is formed in the first opening and a second top layer of the first crystalline structure is formed in the second opening. An unreacted portion of the reactive layer remains on the capping layer. The unreacted portion of the reactive layer is removed. The first crystalline structure is transformed to a second crystalline structure. The capping layer is removed. The second layer is etched by using the second top layer as an etching mask. The first layer is etched by using the first and second top layers as etching masks. As a result, first and second patterns are formed under the first and second top layers, respectively. The first pattern comprises the first top layer and the first layer. The second pattern comprises the second top layer, the first layer and the second layer.
According to another aspect of the invention, a non-volatile memory device is provided. The device comprises a gate electrode formed in a peripheral area. The gate electrode is formed of a first polysilicon layer and a first metal silicide layer. The first metal silicide layer is formed on the first polysilicon layer. A control gate electrode is formed in a cell array area. The control gate electrode is formed of a second polysilicon layer and a second metal silicide layer. The second metal silicide layer is formed on the second polysilicon layer. A floating gate electrode is formed under the control gate electrode. The floating gate electrode is formed of the first polysilicon layer. An inter-gate dielectric layer intervenes between the control gate electrode and the floating gate electrode. A select line is formed in the cell array. The select line is formed of the first polysilicon layer and the first metal silicide layer. The first metal silicide layer includes a substantially vertical portion.
Accordingly, it is possible to use metal silicide layers in a non-volatile memory device. Therefore, it is possible to significantly reduce resistance of the gate electrode, the select line and the control gate electrode, thereby enhancing performance of the device.
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patent: 5472892 (1995-12-01), Gwen et al.
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patent: 5789294 (1998-08-01), Choi
patent: 5869396 (1999-02-01), Pan et al.
patent: 6057218 (2000-05-01), Yu et al.
patent: 6107096 (2000-08-01), Mikagi
Chaudhan Chandra
Marger & Johnson & McCollom, P.C.
Samsung Electronics., Ltd.
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