Non-volatile memory device and method of operating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S267000

Reexamination Certificate

active

07863673

ABSTRACT:
A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

REFERENCES:
patent: 6768158 (2004-07-01), Lee et al.
patent: 6903967 (2005-06-01), Mathew et al.
patent: 7402862 (2008-07-01), Choi et al.
patent: 7723188 (2010-05-01), Kim et al.
patent: 2006/0270156 (2006-11-01), Kim et al.
patent: 1020030020644 (2003-03-01), None
patent: 1020040104144 (2004-12-01), None
patent: 1020050112029 (2005-11-01), None
patent: 1020060031428 (2006-04-01), None
patent: 1020060038129 (2006-05-01), None
Yong Kyu Lee, Tae-Hun Kim, Sang Hoon Lee, Jong Duk Lee and Byung-Gook Park “Twin-Bit Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memory by Inverted Sidewall Patterning (TSM-ISP),”IEEE Transactions on Nanotechnology, vol. 2, No. 4, Dec. 2003. pp. 246-252.
Chiu-Chiao Chung, Hongchin Lin, You-Min Shen and Yen-Tai Lin, “A Multilevel Sensing and Program Verifying Scheme for Bi-NAND Flash Memories,” 2005 IEEE VLSI-TSA International (2005) pp. 267-270.
Takahiko Hara et al., “A 146-mm2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology,”IEEE Journal of Solid-state Circuits, vol. 41, No. 1 (Jan. 2006) pp. 161-169.
Tsu-Jae King, Future Directions: Taking Silicon to the Limit: Challenges and Opportunities, The Electrochemical Society Interface, Spring 2005. pp. 38-40.
Donald A. Neamen, Semiconductor Physics and Devices 3rd edition, (2003) pp. 346-347.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Non-volatile memory device and method of operating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile memory device and method of operating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory device and method of operating the same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2705622

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.