Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-12-18
2007-12-18
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C365S189080
Reexamination Certificate
active
11297052
ABSTRACT:
A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell. The page buffer also includes a second latch unit including a second latch circuit and coupled to the sensing line, the second latch unit being configured not to be activated during the copy-back operation and be activated during program, read, and verification operations, the second latch unit configured to receive data to be programmed in the memory cells and store the data during the program operation, the second latch unit configured to read the data programmed in the memory cells and store the read data during the read and verification operations.
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Hynix / Semiconductor Inc.
Nguyen Viet Q.
Townsend and Townsend / and Crew LLP
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