Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-01
2004-01-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S588000
Reexamination Certificate
active
06677639
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2001-44054, filed on Jul. 21, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and fabrication methods thereof and, more particularly, to floating trap type non-volatile memory devices and to fabrication methods thereof.
BACKGROUND OF THE INVENTION
A non-volatile memory device is an advanced type of memory device that retains information stored in its memory cells even when no power is supplied. Nowadays, the non-volatile memory device is widely used in various kinds of electronic products like as a cellular phone, a memory card and so on.
As one of the non-volatile memory devices, a floating trap type non-volatile memory device comprises a gate electrode, a semiconductor substrate and a floating trap region. The floating region is interposed between the gate electrode and the substrate. During device operation to store or erase date, electrons are trapped into the floating region or discharged from the floating region.
FIG. 1
is a schematic plan view illustrating a typical floating trap type non-volatile memory device.
FIGS. 2 through 5
are cross-sectional views illustrating successive process steps for forming a conventional non-volatile memory device.
FIGS. 2 through 5
are taken along a line I-I′ of FIG.
1
.
FIGS. 1 through 5
are drawings specifically illustrating a cell array area of the non-volatile memory device.
Referring to
FIG. 2
, a floating layer
108
, a lower conductive layer
110
and a mask layer
112
are sequentially formed on a semiconductor substrate
100
. The floating layer
108
comprises a lower dielectric layer
102
, a charge storage layer
104
and an upper dielectric layer
106
. Photoresist patterns
114
are formed on the mask layer
112
.
Referring to
FIGS. 1 and 3
, the mask layer
112
, the lower conductive layer
110
, the floating layer
108
and the substrate
100
are continuously etched to form trenches
118
, floating regions
108
a
, lower conductive strips
110
a
and masks
112
a
, wherein the photoresist patterns
114
are used as etching masks. The trenches
118
define active regions
116
in the substrate
100
. Each of the floating strips, i.e., floating regions
108
a
comprises a lower dielectric strip
102
a
, a charge storage strip
104
a
and an upper dielectric strip
106
a
. Subsequently, the photoresist patterns
114
are removed and an isolation layer
120
is formed to fill the trenches
118
.
Referring to
FIGS. 1 and 4
, a portion of the isolation layer
120
is removed to expose top surfaces of the masks
112
a
to form isolation regions
120
a
in the trenches
118
.
Referring to
FIGS. 1 and 5
, the masks
112
a
are removed. Subsequently, an upper conductive layer is formed on the whole surface of the resultant structure. The lower conductive strips
110
a
and the upper conductive layer are patterned to form gate electrodes
124
. The gate electrodes
124
are disposed across the trenches
118
and the active regions
116
. Each of the gate electrodes
124
comprises a lower gate electrode
110
b
and an upper gate electrode
122
. The upper gate electrode
122
is disposed across the trenches
118
and the active regions
116
. The lower gate electrode
110
b
is located only between the upper gate electrode
122
and the floating strips
108
a.
Though not shown in the drawings, the floating regions, i.e., floating strips
108
a
optionally may be patterned by self-alignment techniques to the gate electrodes
124
thereby to form floating patterns
108
b
, which is located only between the gate electrode
124
and the active regions
116
. Each of the floating patterns
108
b
comprises a lower dielectric pattern
102
b
, a charge storage pattern
104
b
and an upper dielectric pattern
106
b.
According to the conventional non-volatile memory device, the charge storage region i.e., the charge storage strip
104
a
or the charge storage pattern
104
b
has a high defect density on the sidewall thereof. This is due to an etching damage on the sidewall during the formation of the trenches
118
. The defects on the sidewall of the charge storage region may act as leakage current paths at the boundary region between the isolation region and the floating region. Therefore, the stored charges in the charge storage region may be lost through the defects.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a floating region, wherein leakage current is substantially suppressed at the boundary region between an isolation region and the floating region, so that charge loss is substantially suppressed at the boundary region.
It is another object of the present invention to provide a method for fabricating a semiconductor device having a floating region, wherein leakage current is substantially suppressed at the boundary region between an isolation region and the floating region, so that charge loss is substantially suppressed at the boundary region.
According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a gate electrode formed on a substrate. A floating region is interposed between the substrate and the gate electrode. The width of the floating region is wider than that of the gate electrode. The floating region comprises a charge storage region and the width of the charge storage region is wider than that of the gate electrode. The charge storage region is preferably formed of an oxidation resistive layer. The floating region is preferably formed of an ONO layer and the charge storage region is preferably formed of a silicon nitride layer of the ONO layer. The gate electrode comprises a lower gate electrode and an upper gate electrode. The width of the charge storage region is wider than that of the lower gate electrode. An isolation region defines an active region in the substrate. The upper gate electrode is extended across the isolation region and the active region. And, the lower gate electrode is interposed between the upper gate electrode and the active region.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises an isolation region formed on a substrate. The isolation region defines an active region in the substrate. A gate electrode is formed on the active region. A floating region is interposed between the active region and the gate electrode. The width of the floating region is wider than that of the active region. The floating region comprises a charge storage region and the width of the charge storage region is wider than that of the active region. The charge storage region is preferably formed of an oxidation resistive layer. The floating region is preferably formed of an ONO layer and the charge storage region is preferably formed of a silicon nitride layer of the ONO layer. The isolation region fills a trench in the substrate. The isolation region comprises a thermally grown trench oxide at the sidewall of the trench. The gate electrode comprises a lower electrode and an upper electrode. The upper gate electrode is extended across the isolation region and the active region. And the lower gate electrode is interposed between the upper gate electrode and the active region.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises an isolation region on a substrate. The isolation region defines an active region in the substrate. A gate electrode is formed on the active region. A floating region is interposed between the active region and the gate electrode. The floating region has a protrusion portion at an end thereof. The protrusion portion extends into the isolation region and the isolation region substantially surrounds the protrusion portion. The floating region comprises a charge storage region and the charge storage region has the protrusion portion at
Choi Jung-Dal
Hur Sung-Hoi
Lee Chang-Hyun
You Byung-Kwan
Marger & Johnson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
Vu David
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