Non-volatile memory device and fabricating method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S267000, C438S596000

Reexamination Certificate

active

11019304

ABSTRACT:
The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.

REFERENCES:
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patent: 6743675 (2004-06-01), Ding
patent: 6838342 (2005-01-01), Ding
patent: 6884679 (2005-04-01), Park et al.
patent: 6911370 (2005-06-01), Wang et al.
patent: 2005/0224860 (2005-10-01), Hendriks et al.
Edward S. Yang, “Microelectronic Devices”, McGraw-Hill Book Company, 1988, pp. 341-353.

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