Non-volatile memory circuit

Details Non-volatile memory circuit Non-volatile memory circuit

2002-01-07

2003-07-01

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S156000, C365S149000

Reexamination Certificate

active

06587368

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory circuit, and more particularly relates to a non-volatile memory circuit.
BACKGROUND OF THE INVENTION
Integrated circuit memories have come into extensive use in many applications, and particularly in computer systems. It has been a pronounced technological trend to increase the capacity and density of such memories. As manufacturing and design techniques have improved, the cost of memory circuits has decreased dramatically, and this has greatly expanded the number of applications and the size of the market. There are essentially two types of data memory devices used in computers today, “Nonvolatile” and “Volatile”. Common nonvolatile memory devices include the well-known Read Only Memory (ROM) devices that include EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, and Flash EEPROM devices. These nonvolatile memory devices maintain the data stored therein, even when power to the device is removed, and thus they are nonvolatile. Volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices. RAM devices in the prior art have been used for temporary data storage, such as during data manipulation, since writing data into, and reading data out of, the device is performed quickly and easily. However, a disadvantage of these devices is that they require the constant application of power, such as in the form of a data refresh signal, to refresh and maintain data stored in the memory cells of the chip. Once power supplied to the device is interrupted, the data stored in the memory cells of the chip is lost.
SRAM having fast data access speed and long lifetime in all of the memory devices is suitable for use in computers, such as in BIOS.
FIG. 1
illustrates a circuit diagram of a conventional static RAM
100
. The static AM
100
includes two n-channel MOS transistors
104
,
105
and two p-channel MOS transistors
106
,
107
. A pair of nodes A and B is cross-coupled to the gate electrodes of MOS transistors
104
to
107
(flip-flop structure). This cross-coupled arrangement produces a regenerative effect which drive the nodes A and B to opposite voltage states. When one node is high the other is low. The circuit
100
therefore has two data states. A node C is set at the V
ss
level of zero volts. A further node D couples to a full V
dd
source. The source-drain paths of access MOS transistors
108
and
109
couple internal nodes A and B, respectively, to bit lines
102
and
103
. The gate electrodes of access MOS transistors
108
and
109
are coupled to word line
101
.
FIG. 2
illustrates a reading and writing waveform diagram of a static RAM
100
. When writing logic “1” into the static RAM
100
, the voltage state of word line
101
and bit line
102
keep in high level. The high state at node B causes MOS transistor
107
to be turned off and MOS transistor
105
to be turned on. This pulls node A to a low voltage state and bit line
103
is also in a low voltage state. The low state at node A permits MOS transistor
106
to be on while keeping MOS transistor
104
turned off. This further causes node B to be pulled to a high voltage state through MOS transistor
106
. A logic “1” state for the static RAM
100
is arbitrarily defined to be node B high and node A low. When reading logic “1” from the static RAM
100
, bit line
103
and
102
are first set in predetermined voltage state. Then, a high voltage is applied to the word line
101
. At this time, the predetermined voltage state of bit line
103
is pulled down from MOS transistors
105
and
109
. A data reading circuit (not shown in
FIG. 2
) detects a voltage difference between the bit lines
102
and
103
and enlarges the difference to read out the storing data, logic “1”.
When writing logic “0” into the static RAM
100
, the voltage state of word line
101
and bit line
103
are maintained at a high level. The high state at node A causes MOS transistor
106
to be turned off and MOS transistor
104
to be turned on. This pulls node B to a low voltage state and bit line
102
is also in a low voltage state. The low state at node B permits MOS transistor
107
to be on while keeping MOS transistor
105
turned off. This further causes node A to be pulled to a high voltage state through MOS transistor
107
. A logic “0” state for the static RAM
100
is arbitrarily defined to be node A high and node B low. When reading logic “0” from the static RAM
100
, bit lines
103
and
102
are first set in a predetermined voltage state. Then, a high voltage is applied to the word line
101
. At this time, the predetermined voltage state of bit line
102
is pulled down from MOS transistors
104
and
108
. A data reading circuit (not shown in
FIG. 2
) detects a voltage difference between bit lines
102
and
103
and enlarges the difference to read out the storing data, logic “0”.
However, the low cost, large capacity static RAM circuits now in use have volatile memory storage, that is, the data stored in these memories is lost when the power is removed. There are many applications that could be enhanced if low cost memories could be made which were non-volatile. In certain applications, it is essential that the data be retained in the memory when power is removed. Therefore, an additional nonvolatile memory device, such as a hard disk, is needed to store data before power is turned off. If SRAM and nonvolatile memory device can be combined, the memory device will have both advantages of a SRAM and a nonvolatile memory device, such as fast data access, long lifetime and data retention. A nonvolatile SRAM would be useful and worthwhile. Therefore, from the foregoing, it can be seen that a need exists for non-volatile memory storage having low cost and high density of memory storage.
SUMMARY OF THE INVENTION
The conventional static RAMS, while having the advantage of being randomly accessible, have the disadvantage of being volatile. That is, when power is removed from the memories, the data dissipates. The voltage used to preserve the flip-flop states in the static RAM memory cells drops to zero so that the flip-flop loses its data. Therefore, the static RAMS according to the present invention uses ferroelectric capacitors for memory cells that have a significant advantage of being non-volatile. In normal operation, the memory circuit is fully function as a static RAM, and may be accessed quickly. After the power is turned off, the information stored in the volatile portion is copied into the ferroelectric capacitors. The memory circuit is a non-volatile memory circuit.
The ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them. A ferroelectric material has two different stable polarization states and can store the polarization state even though the applied voltage is removed. By assigning a binary zero to one polarization state and a binary one to the other polarization state, ferroelectric capacitors can be used to store binary information. Therefore, according to the present invention, the data of the static RAMS is restored into the ferroelectric capacitors. The advantage of this arrangement is that even though power may be interrupted or removed from the memory, data will continue to be stored.
According to the present invention providing a new memory circuit design, a conventional static RAMS is combined with a ferroelectric capacitors circuit, with the resulting circuit having the advantages of non-volatile characteristics and fast, random writing and reading of data. The memory circuit according to the present invention comprises two MOS transistor circuits to form a CMOS flip-flop circuit and two ferroelectric capacitors. The two ferroelectric capacitors are coupled in series to form a common node C between the two ferroelectric capacitors, and two poles each correspond uniquely to only one respective ferroelectric capacitor. According to the preferred embodiment, both the MOS transistor circuits are c

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