Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-05-11
2001-06-12
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185290
Reexamination Certificate
active
06246608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory circuit and, more particularly, to a non-volatile memory circuit capable of shortening the erasure time for a flash memory which uses memory cells having floating gates.
2. Related Art
A flash memory or non-volatile memory which uses memory cells having floating gates can retain recorded information even when it is powered off and has a faster reading speed than a hard disk or the like. In programming (or writing) memory cells having floating gates, for example, charges are injected into the floating gates to raise the threshold voltages of cell transistors, thereby recording data “0”. In an erasing operation, charges are drawn out of the floating gates to reduce the threshold voltage of cell transistors, causing data “1” to be recorded.
The injection and drawing of charges into and out of the floating gates needs a specific time so that changing data takes time if such charge injection and drawing are performed cell by cell. To cope with this shortcoming, in program mode, the conventional memory circuits temporarily render all the memory cells in an erased state which is data “1”, then inject charges only to desired or target memory cells to write data “0” there. In the erasing operation, charges are temporarily injected to all the memory cells of data “1” to make all of their threshold voltages in a high state (preprogram) and an erase voltage is simultaneously applied to all the memory cells to render them in a state of data “1” (collective erasure).
As apparent from the above, a flash memory or nonvolatile memory which uses memory cells having floating gates stores given information by changing the state of the target memory cells to data “0” from data “1” in program mode, and preprograms and collectively and simultaneously erase all the memory cells to a state of data “1” in erasing mode.
FIG. 1
is a schematic operational chart of a conventional memory; the horizontal scale represents the number of cells and the vertical scale threshold levels (threshold voltages) and data “1” and “0” of cell transistors. Shown horizontally are (1) erased state (initial state), (2) first writing, (3) first erasing, (4) second writing and (5) second erasing.
The diagram shows a reference voltage (Vref) for writing and erasure. In an ordinary memory circuit, a sense amplifier compares the output voltage corresponding to a cell transistor with the reference voltage. When the threshold voltage of a cell transistor is higher, the cell transistor has a small current value and provides a high output voltage, and when the threshold voltage of the cell transistor is lower, the cell transistor has a large current value and provides a low output voltage. The comparison of the threshold voltage with the reference voltage for the sense amplifier should actually be discussed in connection with the output voltage. As the high/low state of the threshold voltage of each cell transistor corresponds one to one to the high/low state of the output voltage, however, the reference voltage Vref in the cell is used as the reference voltage corresponding to the threshold voltage in the following explanation of this specification. Therefore, changing the setting of the reference voltage in a cell is the same as changing the setting of the reference voltage for the sense amplifier. It is to be noted however that while the high/low states of both reference voltages correspond to each other, their absolute values may differ from each other in some cases.
FIGS. 2A and 2B
are diagrams illustrating the transition of data and threshold levels (threshold voltages) of a 4×4 memory cell array in accordance with the operations in FIG.
1
.
FIG. 2A
shows the transition of data, and
FIG. 2B
the transition of the threshold levels of cell transistors. The numerals “0” and “1” in the individual cells in
FIG. 2A
respectively indicate data “0” and “1”, and the numerals “0” and “1” in the individual cells in
FIG. 2B
respectively indicate a low threshold level Vth1 and a high threshold level Vth2.
In the initial state (1), the threshold levels of all the cell transistors are the low level vth1, so that data of all the cell transistors are “1”. In the first writing, charges are injected to the floating gates of the target memory cells to set their threshold levels to the high level Vth2. Accordingly, some of the cells are in the state of the high threshold level Vth2 (data “0”), while the other cells are in the state of the low threshold level Vth1 (data “1”).
To implement the second writing (4), erasure is carried out temporarily. That is, in this first erasing (3), those cells which have had the low threshold level Vth1 in the aforementioned state (2) are individually preprogrammed to all have the high threshold level Vth2. Then, the erase voltage is simultaneously applied to all the memory cells to draw the charges from the floating gates, rendering all the cell transistors to have the low threshold level Vth1 (data “1”). In this situation, the second writing (4) is performed to apply a write voltage to target cell transistors to inject charges to their floating gates so that those cell transistors of target memory cells to set their have the high threshold level Vth2 (data “0”).
Thereafter, when data rewriting becomes necessary again, the second erasing (5) is executed in the same manner discussed above to render all the cell transistors to have the low threshold level Vth1 (data “1”).
The conventional non-volatile memories need to erase all the cell transistors or all the cell transistors in a given sector, every time data is to be rewritten. This erasing operation involves preprogramming and simultaneous erasure and thus takes time. It is undesirable to implement such long and power-consuming erasure every time data is to be rewritten. To rewrite image data in a digital camera, for example, such an erasing operation takes time and suffers increased power consumption.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a non-volatile memory circuit which is free of the conventional problem.
It is another object of this invention to provide a non-volatile memory circuit which performs a simpler erasing operation at the time of data rewriting.
It is a further object of this invention to provide a non-volatile memory circuit which can quickly carry out an erasing operation at the time of data rewriting.
It is a still further object of this invention to provide a non-volatile memory circuit which can reduce power consumption needed in an erasing operation at the time of data rewriting.
To achieve the above objects, according to one aspect of this invention, there is provided a non-volatile memory circuit which stores information by altering a threshold voltage of memory cells so as to associate first and second threshold voltages respectively with first and second data values, and which has a first recorded state and a second recorded state different from the first recorded state such that in the first recorded state, the first and second threshold voltages are lower or higher than a first reference voltage, and in the second recorded state, the first and second threshold voltages are lower or higher than a second reference voltage different from the first reference voltage. The first or second reference voltage is set in accordance with the first and second recorded states.
With the above structure, in the first recorded state, the first and second threshold voltages are either lower or higher than the first reference voltage within a voltage range lower or higher than the second reference voltage. At the time of transition to the second recorded state from the first recorded state, the use of the second reference voltage renders all of those cell transistors which have been in the first recorded state to have a threshold voltage lower or higher than the second reference voltage so that an erasing operation has virtually been carried out with respect to the second referenc
Arent Fox Kintner & Plotkin & Kahn, PLLC
Dinh Son T.
Fujitsu Limited
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