Non-volatile memory cells having floating gate and method of...

Details Non-volatile memory cells having floating gate and method of... Non-volatile memory cells having floating gate and method of...

2005-09-13

2005-09-13

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

06943403

ABSTRACT:
A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.

REFERENCES:
patent: 6469341 (2002-10-01), Sung et al.
patent: 6670239 (2003-12-01), Yoon
patent: 6727545 (2004-04-01), Wang et al.
patent: 3-34577 (1991-02-01), None
patent: 1997-18737 (1997-04-01), None
English Abstract Only***.

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