Non-volatile memory cell with a single level of polysilicon,...

Details Non-volatile memory cell with a single level of polysilicon,... Non-volatile memory cell with a single level of polysilicon,...

2000-10-06

2002-06-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

06410389

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile memory cell with a single level of polysilicon, in particular of the flash EEPROM type, and to a method for manufacturing this cell.
BACKGROUND OF THE INVENTION
As is known, the semiconductors market is requiring, increasingly more urgently, memory devices which are embedded in other electronic devices, for example advanced-logic devices such as microprocessors. In this type of application, it is necessary firstly to guarantee the functionality and reliability of the memory device, and secondly to keep unchanged as far as possible the performance of the advanced-logic device, on the technological platform and the macro-cell libraries on which the manufacturing methods of the incorporated devices are founded and based. These methods additionally require reduction as far as possible of the method steps which are in addition to those commonly used for production of the advanced-logic devices. In order to achieve this, it is therefore necessary to have memory cells which are highly compatible with the production methods for these advanced-logic devices, with consequent lower production costs; the circuitry which makes the cells function must also be more efficient and simple.
At present, for this purpose, inter alia, memory cells with a single level of polysilicon are used.
FIGS. 1
,
2
and
3
show in detail a memory cell
2
of the flash EEPROM type, with a single level of polysilicon included in a memory device
1
, comprising a substrate
3
of semiconductor material with a first type of conductivity, and in particular P.
The memory cell
2
comprises a diffuse control gate region
6
, with a second type of conductivity, in particular N, formed in the substrate
3
, in a first active region
30
delimited by field oxide portions
10
; regions of source
4
a
,
4
b
and drain
5
a
,
5
b
of type N, formed in the substrate
3
, in a second active region
31
, which is also delimited by field oxide portions
10
, and is adjacent to the first active region
30
; a gate oxide region
7
which covers the first active region
30
, and a tunnel oxide region
8
, which is less thick than the gate oxide region
7
, and covers the second active region
31
.
A floating gate region
9
, made of polycrystalline silicon, extends transversely relative to the first
30
and to the second
31
active regions; in the first active region
30
, the floating gate region
9
is isolated from the diffuse control gate
6
by means of the gate oxide region
7
, whereas in the second active region
31
, the floating gate region
9
is isolated from the substrate
3
and from the regions of source
4
a
,
4
b
and drain
5
a
,
5
b
, by means of the tunnel oxide region
8
. Laterally relative to the floating gate region
9
, spacers
11
,
12
made of isolating material are provided.
FIGS. 4
to
7
b
show in succession some steps of the method for production of the memory cell
2
.
FIGS. 4
,
5
a
,
6
a
,
7
a
,
8
a
are cross-sectional views along line II—II of FIG.
1
and
FIGS. 5
b
,
6
b
,
7
b
,
8
b
are cross-sectional views along line III—III of FIG.
1
.
In greater detail, starting from the substrate
3
, after portions of field oxide
10
have been grown (FIG.
4
), a layer of photo-sensitive material is deposited, in order to produce a capacitive implant mask
40
, which leaves bare the first active region
30
and portions of the second active region
31
. Then, using the mask
40
, the diffuse control gate region
6
and the regions of source
4
a
and drain
5
a
are formed in the first
30
and in the second
31
active regions, by means of implantation and subsequent diffusion of a doping material, which is typically arsenic or phosphorous (
FIGS. 5
a
,
5
b
). The gate oxide
7
and tunnel oxide
8
regions are then produced in the active regions
30
and
31
.
A polycrystalline silicon layer is then deposited and removed selectively, in order to define the floating gate region
9
of the memory cell
2
(
FIGS. 7
a
,
7
b
).
The method then continues with formation of the self-aligned regions of source
4
b
and drain
5
b
, and with formation of the floating gate region
9
and of the spacers
11
and
12
(FIG.
3
).
Although it is advantageous in various respects, the known memory cell has the disadvantages that it is not highly compatible with the new methods for production of the electronic devices in which the memory device
1
is incorporated, and it requires complex circuitry in order to function, and is thus costly to produce. In particular, during erasure, it is necessary to generate and transfer a high voltage (for example of up to 16 V) to the source region of the cell, which involves considerable difficulties.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a non-volatile memory cell with a single level of polysilicon. The non-volatile memory cell includes a substrate of semiconductor material, a control gate region, source and drain regions, and a floating gate region. The substrate has a first type of conductivity and includes first and second active regions adjacent to each other. The source and drain regions have a second type of conductivity and are formed in the second active region. The floating gate region extends above the substrate and transversely relative to the first and second active regions. The control gate region has the second type of conductivity and is formed in a triple-well structure in the first active region. The triple-well structure includes an isolation region having the second type of conductivity and an isolated region having the first type of conductivity. The isolated region surrounds the control gate region is enclosed below and laterally by the isolation region.


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