Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-09
2005-08-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C257SE21625, C257SE29309
Reexamination Certificate
active
06927136
ABSTRACT:
A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.
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Hsieh Kuang-Yeu
Liu Ruichen
Lung Hsiang-Lan
Tseng Jiun-Yi
Wu Tai-Bor
Fourson George
Jiang Chyun IP Office
Macronix International Co. Ltd.
Pham Thanh V.
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