Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-07
2011-06-07
Malsawma, Lex (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C257SE21180
Reexamination Certificate
active
07955935
ABSTRACT:
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.
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Prall Kirk D.
Sandhu Gurtej S.
Brooks Cameron & Huebsch PLLC
Huber Robert
Malsawma Lex
Micro)n Technology, Inc.
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