Non-volatile memory cell device and methods

Details Non-volatile memory cell device and methods Non-volatile memory cell device and methods

2011-03-01

2011-03-01

Malsawma, Lex (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S288000, C257SE21180

Reexamination Certificate

active

07897470

ABSTRACT:
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

REFERENCES:
patent: 5714766 (1998-02-01), Chen et al.
patent: 6319774 (2001-11-01), Hai
patent: 6331463 (2001-12-01), Chen
patent: 6762093 (2004-07-01), Rudeck
patent: 6906377 (2005-06-01), Ni et al.
patent: 6913984 (2005-07-01), Kim et al.
patent: 6970053 (2005-11-01), Akram et al.
patent: 7005697 (2006-02-01), Batra et al.
patent: 7057940 (2006-06-01), Hsu et al.
patent: 7092287 (2006-08-01), Beulens et al.
patent: 7119395 (2006-10-01), Gutsche et al.
patent: 7208793 (2007-04-01), Bhattacharyya
patent: 7446371 (2008-11-01), Kim
patent: 2003/0235064 (2003-12-01), Batra et al.
patent: 2005/0095786 (2005-05-01), Chang et al.
patent: 2005/0202639 (2005-09-01), Yoo et al.
patent: 2006/0003531 (2006-01-01), Chang et al.
patent: 2006/0014329 (2006-01-01), Park et al.
patent: 2006/0081911 (2006-04-01), Batra et al.
patent: 2008/0121969 (2008-05-01), Sandhu et al.
patent: 2008/0121976 (2008-05-01), Sandhu et al.
patent: 1 411 555 (2004-04-01), None
patent: 1 418 625 (2004-05-01), None
patent: 1 437 775 (2004-07-01), None
patent: 1 737 033 (2006-12-01), None
patent: 2005036599 (2005-04-01), None
patent: 2005101488 (2005-10-01), None
patent: 2006007069 (2006-01-01), None
patent: 2008019039 (2008-02-01), None
International Prelimary Patentability Report for related PCT Application Serial No. PCT/US2007/017297 which claims priority to U.S. Appl. No. 11/513,933, filed Aug. 31, 2006, 13 pgs.
IC Knowledge, LLC, “Technology Backgrounder: Atomic Layer Deposition”, 7 pgs (2004).
Winkler, O, et al, “Semiconductor Nanocrystals vol. 1”, Silicon Nanodot fabrication and application in nonvolatile memories, B. Podor, et al. editors, pp. 190-196 (Sep. 2005).

Affiliated with

Also associated with

Rating

Non-volatile memory cell device and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile memory cell device and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory cell device and methods will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2621238