Non-volatile memory cell array having common drain lines and...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185180, C365S185290

Reexamination Certificate

active

11038726

ABSTRACT:
A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

REFERENCES:
patent: 5999444 (1999-12-01), Fujiwara et al.
patent: 6370064 (2002-04-01), Kim
patent: 6501681 (2002-12-01), Van Buskirk et al.
patent: 6720614 (2004-04-01), Lin et al.
patent: 01-102748 (2001-11-01), None
patent: 03-34327 (2003-05-01), None
patent: 10-2003-0094497 (2003-12-01), None

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