Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reissue Patent
2005-01-11
2008-10-07
Tran, Long K. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S390000, C257S391000, C257SE21660
Reissue Patent
active
RE040532
ABSTRACT:
Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017cm−3.
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Hofmann Franz
Kohlhase Armin
Ludwig Christoph
Willer Josef
Greenberg Laurence A.
Locher Ralph E.
Qimonda Flash GmbH
Stemer Werner H.
Tran Long K.
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