Non-volatile memory and method of fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S558000, C438S561000

Reexamination Certificate

active

07572691

ABSTRACT:
A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

REFERENCES:
patent: 5460987 (1995-10-01), Wen et al.
patent: 5668031 (1997-09-01), Hsue et al.
patent: 6458677 (2002-10-01), Hopper et al.
patent: 7352631 (2008-04-01), Burnett et al.

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