Non-volatile memory and accelerated test method for address...

Details Non-volatile memory and accelerated test method for address... Non-volatile memory and accelerated test method for address...

2002-06-28

2010-02-16

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S720000, C257S296000, C257S390000, C365S094000, C365S201000

Reexamination Certificate

active

07664998

ABSTRACT:
A modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells do not require much effort during manufacturing and use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a ‘0’, into this pair and vice versa. During test, a simple and therefore only minimal time requiring pattern, preferably a checkerboard pattern, is written into and read from the non-volatile memory, allowing a quick determination of the decoders' correct function.

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Mitsumoto, Toshio, English Translation from JPO website of JP 05189988 A. pp. 1-9.

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