Non volatile embedded memory with poly protection layer

Details Non volatile embedded memory with poly protection layer Non volatile embedded memory with poly protection layer

2002-09-24

2004-09-07

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S275000

Reexamination Certificate

active

06787416

ABSTRACT:

BACKGROUND OF THE INVENTION
In non-volatile memory production, an electron trap layer comprising ONO is easily damaged during formation of periphery devices. The non-volatile memory cells and ONO layer typically are formed before CMOS processing used to form peripheral devices, exposing the cells to thermal damage. The thermal cycles in CMOS processing also cause dopants used in buried bit lines to diffuse, which limits the manufacturer's ability to shrink feature sizes.
Accordingly, an opportunity arises to devise methods and structures that reduce damage to an electron trapping layer and to reduce thermal exposure during CMOS processing.
SUMMARY OF THE INVENTION
The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.


REFERENCES:
patent: 6033958 (2000-03-01), Chou et al.
patent: 6087225 (2000-07-01), Bronner et al.
patent: 6207509 (2001-03-01), Inoue
patent: 6346442 (2002-02-01), Aloni et al.
patent: 6551884 (2003-04-01), Masuoka

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