Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-10-21
2001-04-24
Whitehead, Jr., Carl (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S300000, C257S305000, C257S306000, C257S308000, C257S311000, C257S068000, C257S071000
Reexamination Certificate
active
06222216
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to electronic memories, and in particular, to non-volatile memory fabricated using a dynamic memory process, and systems and methods using the same.
BACKGROUND INFORMATION
As semiconductor technology has advanced, data processing applications have also rapidly evolved to provide personal services to individual users. Such data processing applications include personal digital assistants (PDA), personal digital communicators (PDC), pocket schedulers, and the like. In implementing such data processing application, a dynamic random access memory and a read-only memory are generally used to provide the proper storage devices required for operation of these data processing applications. For example, the read-only memory (ROM) is typically utilized to store an operating system (OS) for the data processing application. As well, the dynamic random access memory (DRAM) may provide the necessary data memory and read-write memory required when performing operations within the data processing system.
While both DRAM and ROM memories are needed to implement most data processing applications, the methodologies utilized to fabricate each of these types of data processing systems are quite different and it is therefore not optimal to use one technique to build both types of memory on the same integrated circuit chip. As is well-known in the semiconductor art, ROM memories are typically implemented using either diffusion programming, gate programming, or metal programming techniques. Metal programming techniques selectively pattern metal conductors within the ROM to program that memory in accordance with the user's needs. Metal programming is particularly attractive as it is typically performed late in the ROM fabrication processing stage and, therefore, allows a designer of the memory system or a CPU or a microcontroller, to modify or create new programming code for an application late in the manufacturing process. However, while metal programming has such useful characteristics and is often used during ROM programming, metal programming is difficult to implement in a DRAM manufacturing process is utilized as process. Among other things, the normal number of metal layers which can be fabricated is limited, for the most part, to two in DRAMs. However, two metal layers are often insufficient to provide the desired number of metal layers required for ROM programming.
In addition to metal programming, gate programming may be utilized to program a ROM. When a ROM is programmed using the gate programming technique, the gate for the ROM memory cell is formed approximately during a mid-point of the processing steps. In contrast, a gate is formed in a DRAM during the initial steps of the DRAM manufacturing process because a capacitor utilized in a DRAM cell is then built on top of the gate. Thus, a DRAM process does not result in an optimal methodology for implementing gate programmed ROMs.
Furthermore, diffusion programming of ROMs also fails to result in optimal results when a DRAM process is used. In diffusion programming, the transistor drains are selectively implanted or masked in a diffusion process. Specifically, such diffusion programming is inflexible and does not allow a user to re-program or modify an existing program determined by diffusion wells formed during early manufacturing steps.
For these reasons, the DRAMs and ROMs are typically implemented on separate chips in today's (information appliances) and then interconnected to the remainder of the system using a printed circuit board. Because at least two separate integrated circuit chips must then be utilized to provide the desired functionality, the size of resulting products is limited by the dimensional requirements of the two integrated circuit devices, not to mention power and system cost. In a technology where smaller size connotes the desired characteristics of faster speeds and lower power consumption, the requirement that devices be implemented in two separate integrated circuits may have prohibitive overhead costs for some applications. Additionally, if two integrated circuits are utilized to implement both a DRAM and a ROM in a data processing system, the performance of that system will necessarily be limited by the power consumption and speed limitations inherent in the use of two separate devices.
Therefore, a need exists for an integrated circuit that may implement both DRAMs and any non-volatile memory, including ROM, to reduce the power consumption and overhead costs associated with the implementation of two separate integrated circuits in some data processing applications. Additionally, a need exists for a methodology for manufacturing both DRAMs and non-volatile memories on a same integrated circuit in an efficient and reliable manner. Such an implementation can also enhance the “optimization of total memory address space and memory” for an IA (Information Appliance).
SUMMARY OF THE INVENTION
The previously mentioned needs are fulfilled with the present invention. Accordingly, there is provided, in a first form, a method for manufacturing a memory cell. The method includes the steps of forming a first transistor having a first terminal, a second terminal, and a third terminal and forming a first terminal of a first capacitor structure. The first terminal of the first capacitor structure is connected to a first reference voltage and to the first terminal of the first transistor.
Additionally, there is provided, in a second form, a non-volatile memory cell. The non-volatile memory cell includes a first transistor having a first terminal, a second terminal, and a third terminal. The non-volatile memory cell also includes a first capacitor having a first terminal and a second terminal. The first terminal of the capacitor is connected to a first reference voltage and the first terminal of the first transistor.
Furthermore, there is provided, in a third form, a single integrated circuit, including a dynamic random access memory and a non-volatile memory. The non-volatile memory includes a first plurality of memory cells and a second plurality of memory cells. The first plurality of memory cells includes a first transistor having a first terminal, a second terminal, and a third terminal. The first plurality of memory cells also comprises a first capacitor having a first terminal.
The first terminal of the first capacitor is connected to a first reference voltage and the first terminal of the first transistor.
Additionally, there is provided, in a fourth form, a sense amplifier circuit. The sense amplifier circuit includes a first device for selectively enabling the sense amplifier circuit. The sense amplifier circuit also includes a sensing circuit for determining a logic state of a first control signal by determining a differential between the first control signal and a first reference voltage. The sense amplifier circuit also includes a reference device connected to the sensing circuit to provide the first reference voltage. The reference device includes a first transistor connected to the first reference voltage. The first transistor has a high impedance.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to note the drawings are not intended to represent the only form of the invention.
REFERENCES:
patent: 5250827 (1993-10-01), Inoue et al.
patent: 5606193 (1997-02-01), Ueda et al.
patent: 5634102 (1997-05-01), Capps
patent: 5796135 (1998-08-01), Liang et al.
patent: 0 186 855 A2 (1986-07-01), None
patent: 0 636 955 A1 (1995-02-01), None
patent: 56-027958 (1981-03-01), None
patent: 05063162 (1991-08-01), None
Sedra et al., “Read Only Memory (ROM),” Microelectronic Circuits, pp. 965-966, 1991.*
Terawaki Shinji; European Patent Office—Patent Abstracts of Japan; Semiconductor Device; Mar. 18, 1981; Abstract; figures 1-7; vol. 005 No. of 078 (E058); European Patent Office.
Tanaka Kenichi; European Patent Office—Patent Abstracts o
Holland Wayland Bart
Mohan Rao G. R.
Jr. Carl Whitehead
Murphy, Esq. James J.
Silicon Aquarius, Inc.
Warren Matthew E.
Winstead Sechrest & Minick
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