Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-17
2003-01-07
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S308000, C438S528000, C438S530000
Reexamination Certificate
active
06503801
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device with transistors, and to a method of manufacturing the semiconductor device. The present invention has particular applicability in semiconductor devices comprising high density metal oxide semiconductor field effect transistors (MOSFETs) with submicron dimensions.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by various efforts to decrease the size of device element formed in integrated circuits (IC), and such the efforts have contributed in increasing the density of circuit elements and device performance. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Currently, the most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor having uniform conductivity. An input signal is typically applied to the gate electrode via a gate terminal. Heavily doped active regions, e.g., source/drain regions, are formed in the semiconductor substrate and are connected to source/drain terminals. The typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether an active region acts as a source or drain depends on the respective applied voltages and the type of device being made, e.g., PMOS or NMOS. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The channel region is typically lightly doped with an impurity type opposite to that of the source/drain regions, and the impurity concentration profile is substantially uniform from the surface into the substrate, as shown by line A in FIG.
2
. The gate electrodes is generally separated from the semiconductor substrate by an insulating layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In practical MOSFET device, a channel implantation process is frequently performed to augment the substrate doping of the same conductivity. Thus, for an NMOS device, a p-type impurity is ion implanted into the substrate and channel region, and for a PMOS device, an n-type impurity is ion implanted into the substrate and channel region. The threshold voltage is the minimum required voltage applied to the gate electrode of a MOSFET device so as to invert the conductivity of the surface of the semiconductor substrate, forming a conduction channel that is of the same conductivity type as the source and drain regions. As shown by curve A in
FIG. 13
, as the device size shrinks, the channel length decreases and, after some point, the threshold voltage starts to decrease appreciably with the channel length. The decrease of the threshold voltage with the channel length is theoretically predicted, and this phenomenon is known as the “short channel effect (SCE)”.
Contrary to what is normally expected, in modem technologies, it has been observed that a threshold voltage initially increases with decreasing channel length, before the threshold voltage eventually decreases rather sharply, as shown by curve B in FIG.
13
. This phenomenon has been termed “reverse short channel effect (RSCE)” or “threshold voltage roll-off”. Rafferty et al. (IEDM Tech. Dig., pp. 311, 1993) proposed that RSCE is a result of the transient enhanced diffusion of the channel profile induced by source/drain implantation. They explained that the damage by source/drain implantation generates silicon self-interstitials which flow outward and then recombine (annihilated) at the silicon surface under the gate oxide, thereby giving rise to a flux of the channel implant impurity toward the surface and raising the surface concentration of the channel impurity, leading to RSCE. It has been experimentally discovered that RSCE can be avoided by preventing the channel implant from increasing at the surface of a silicon substrate.
Many approaches have been introduce, such as a retrograde channel profile, to control or even eliminate RSCE. The retrograde channel profile has an impurity concentration peak deep under the surface. Conventionally a retrograde channel profile is formed by controlling the ion implantation energy such that an impurity concentration peak is formed at a certain depth below the surface of a semiconductor substrate. However, it is difficult to achieve an optimum retrograde channel profile to reduce RSCE because the implanted impurity atoms easily diffuse toward the substrate surface by the subsequent processing steps, e.g., annealing, thereby resulting in less steep retrograde boron profile in the channel region.
Thus, there is a continuing need for improved method to reduce RSCE and the threshold voltage rolling off.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is simplified, efficient and production worthy methodology for manufacturing a MOSFET device exhibiting less susceptibility to the reverse short channel effects.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantage are achieved in part by a method of manufacturing a semiconductor device, the method comprising: ion implanting atoms into a portion of a main surface of a semiconductor substrate or a well region containing a first conductive type impurity, to form a damage region adjacent to a first side portion of a channel region in the main surface; annealing to diffuse the first conductive type impurity atoms in the channel region and damage region toward an interface region between the channel region and damage region, thereby forming a high impurity region of the first conductive type in the interface region; and ion implanting a second conductive type impurity into the main surface to form a source region overlapping the damage region and adjacent to the first side portion of the channel region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.
REFERENCES:
patent: 5792699 (1998-08-01), Tsui
patent: 5899732 (1999-05-01), Gardner et al.
patent: 6066535 (2000-05-01), Murai
patent: 6136673 (2000-10-01), Frei et al.
patent: 5-190848 (1993-07-01), None
An Judy X.
Ng Che-Hoo
Rouse Richard P.
Advanced Micro Devices , Inc.
Chaudhari Chandra
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