Non-switching pre- and post- disturb compensational pulses

Details Non-switching pre- and post- disturb compensational pulses Non-switching pre- and post- disturb compensational pulses

2006-03-28

2006-03-28

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S185190

Reexamination Certificate

active

07020005

ABSTRACT:
A method of operating a passive matrix addressable ferroelectric device having a voltage pulse protocol with a pre-disturb and post-disturb cycle before and after a disturb generating operation cycle respectively in order to minimize the effect of disturb voltage on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when It is applied for either a write or read operation.

REFERENCES:
patent: 3002182 (1961-09-01), Anderson
patent: 6856534 (2005-02-01), Rodriguez et al.
patent: 6937500 (2005-08-01), Gudesen et al.
patent: 6950330 (2005-09-01), Thompson et al.
patent: 2002/0141225 (2002-10-01), Nakamura
patent: 2003/0179610 (2003-09-01), Sakai
patent: WO-02/05287 (2002-01-01), None

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