Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-12-23
2004-05-04
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S678000, C257S737000, C257S738000, C257S711000, C257S712000
Reexamination Certificate
active
06731012
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor chip packaging. More particularly, the present invention relates to a non-planar semiconductor chip, and a method of forming the non-planar semiconductor chip.
1. Related Art
In the manufacture of semiconductor chip packages, such as laminate chip carriers, differences in the coefficients of thermal expansion, in combination with thermal cycling, tend to produce high stresses in locations of abrupt geometric change within the chip. During thermal cycling the chip may bend creating a stress concentration between the outer edges of the chip and the package cover plate, heat sink, or other device mounted thereon, as well as the adhesive materials therebetween. In addition, high localized stresses tend to occur at the edges of organic chip carrier packages, having heat spreaders or coupled caps, due to the differences in curvature of the various layers. Further, flaws, such as voids, cracks, etc., within the edges or corners of the chip may lead to crack propagation, particularly in locations of abrupt geometric change. As a result, chips may become cracked and/or delamination may occur between the chip, cover plate, and the adhesive material therebetween.
Attempts have been made in the industry to minimize the amount of stress concentrations within the chip packages. For instance, the thickness of the chip has been reduced in an attempt to make the chip more flexible, thereby minimizing the stress concentrations. The thickness of the cover plate or heat sink has been reduced near the edges of the cover plate or heat sink in an attempt to increase flexibility as well. Additionally, attempts have been made to minimize the amount of thermal mismatch between the chip, cover plate or heat sink and the adhesives in contact with the chip.
Accordingly, there currently exists a need in the industry for a semiconductor chip package having reduced stress concentrations therein.
SUMMARY OF THE INVENTION
The present invention provides a non-planar semiconductor chip which reduces the stress concentrations produced within semiconductor chip packages, e.g., at the outer edges of the chip-cap interface, within the adhesive material, etc. The present invention further provides a method of making a semiconductor chip package having a non-planar chip therein.
The first general aspect of the present invention provides an electronic package comprising: an electronic component having a first surface electrically mounted to a substrate and a second arcuate surface having a contour such that the distance between the first surface and the second arcuate surface is greatest substantially near the center of the electronic component. This aspect provides an electronic package having a chip with a non-planar or domed surface which reduces the stress concentrations located at the edges of the electronic package. This aspect further reduces the amount of cracking and delamination that typically occurs within the electronic package, particularly at the edges due to thermal cycling.
The second aspect of the present invention provides a method of forming an electronic package, comprising the steps of: providing an electronic component having a first featurized surface and a second surface; and removing a portion of the second surface such that the second surface is substantially arcuate, having a thickness greatest substantially near the center of the electronic component. This aspect provides similar advantages as those associated with the first general aspect.
The third general aspect of the present invention provides a method of forming a chip, comprising the steps of: providing an electronic component having a first featurized surface and a second planar surface; removing a first portion of the second planar surface forming a first arcuate surface; and removing a second portion of the second planar surface forming a second arcuate surface. This aspect provides similar advantages as those associated with the first general aspect.
The fourth general aspect provides a semiconductor chip having a substantially planar first surface and an arcuate second surface. This aspect provides similar advantages as those associated with the first general aspect.
The fifth general aspect provides a method of forming an electronic package, comprising the steps of: providing an electronic component; and profiling at least one edge of the component. This aspect allows for an electronic component having at least one radiused or profiled edge therein. This provides for the removal of voids, chips or other small defects found at the edges of the chip due to scoring and dicing operations.
The sixth aspect provides an electronic component having at least one substantially planar surface and at least one profiled edge. This aspect provides similar advantages as those associated with the fifth aspect.
The seventh aspect provides an electronic package, comprising: at least one electronic component, having at least one non-planar surface. This aspect provides a chip having either the advantages associated with the domed back surface of the first aspect, or the advantages associated with the radiused edges of the fifth aspect.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.
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Brodsky William L.
Sathe Sanjeev B.
Thiel George H.
International Business Machines - Corporation
Nguyen Dilinh
Pham Long
Schmeiser Olsen & Watts
Steinberg William H.
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