Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-20
2001-05-08
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S653000, C438S637000, C257S762000
Reexamination Certificate
active
06228767
ABSTRACT:
BACKGROUND OF THE INVENTION
In the past, copper interconnects on integrated circuits were not possible due to the diffusion of copper into the silicon substrate that changes the electrical properties of silicon in such a way as to prevent the transistors in the integrated circuits from functioning. Recent developments have proven successful in providing a diffusion barrier between the copper interconnect and the substrate. For example, IBM has developed a damascene process to deposit a diffusion barrier in silicon wafers along with copper. See IEEE Spectrum, January 1998, page 23 and IBM Research, Number 4, 1997, page 17. These developments for the first time allow for the commercial use of copper in integrated circuits.
FIELD OF THE INVENTION
This invention relates to novel copper-based non-linear circuit elements on integrated circuits and processes for making such elements.
SUMMARY OF THE INVENTION
The present invention provides for copper-based non-linear circuit elements on integrated circuits.
Non-linear circuit elements such as copper oxide rectifiers have not been used in integrated circuits, because of previous unsolved problems of copper contaminating the silicon substrate. Because of recent successes in developing effective diffusion barriers between copper and the silicon substrate, the placing of copper-based non-linear circuit elements on integrated circuits are now possible.
Copper oxide rectifiers are used for various purposes including providing a voltage drop and preventing damage of sensitive devices from voltage spikes. These rectifiers are based upon the knowledge that a layer of cuprous oxide on the surface of a copper conductor will permit the passage of electrons from the copper into the oxide, but prevents the passage of electrons from the oxide into the copper.
A number of ways are disclosed herein to manufacture copper-based non-linear circuit elements on integrated circuits.
One method of forming a non-linear circuit element on an integrated circuit comprises the steps of a) applying a diffusion barrier on a substrate; b) depositing a layer of copper onto the diffusion barrier; and c) forming a copper oxide layer on the copper layer. The composition of the copper oxide layer is predominantly Cu
2
O.
Step c) is preferably performed by depositing a layer of copper oxide or by oxidizing at least a part of the copper layer. More particularly, step c) may comprise the steps of applying a dielectric layer onto the layer of encapsulated copper, applying a resist to define the diode region, applying a pattern to the diode resist, etching through the dielectric layer where the resist is not present until at least a portion of the copper is exposed, removing the resist, depositing a diffusion barrier onto the exposed copper and remaining dielectric layer, etching to selectively remove the diffusion barrier on the copper, and applying a copper oxide layer on the exposed copper.
After forming the copper oxide layer on the copper layer, a chemical-mechanical planarization of the copper oxide layer may be performed. Alternatively, an anisotropic etch such as a plasma etch back of the copper oxide layer may be performed. A liner or diffusion barrier is then deposited. A dielectric layer may finally be applied. The composition of the liner and diffusion barrier may be tantalum, tantalum nitride, titanium nitride, tungsten nitride, titanium silicon nitride, molybdenum nitride, tantalum silicon nitride, silicon nitide, Cu
X
Ge
Y
, or CuAl alloy. See Jackson, Broadbent et al., Solid State Technology, March 1998; S. C. Sun, 1997 IEDM; U.S. Pat. Nos. 5,420,069 and 5,430,258, which are all herein incorporated by reference.
The substrate may be preliminarily formed by applying a patterned resist, etching the dielectric layer where the resist is not present, and then removing the resist. A liner is deposited on the substrate. Copper is then deposited on the liner, completely filling narrow trenches but only partially filling wider areas. Copper oxide is then deposited, filling the remaining depth of the wider areas. The manufacture of such a circuit element may comprise the following steps: a) applying a patterned resist on a substrate, b) etching the dielectric layer where the resist is not present, c) removing the resist, d) applying a diffusion barrier on the substrate, e) depositing a layer of copper onto the diffusion barrier, f) forming a copper oxide layer on the copper layer, g) conducting a chemical or mechanical planarization of the copper oxide layer to form a planarized surface, and h) depositing a diffusion barrier layer onto the planarized surface.
Also, in accordance with this invention, an electrical interconnection structure is provided that comprises a) a substrate layer; b) a diffusion barrier on said substrate layer; c) a copper layer on said diffusion barrier; and d) a copper oxide layer on said copper layer. Such an electrical interconnection structure may additionally have a diffusion barrier on the copper oxide layer.
REFERENCES:
patent: 1640335 (1927-08-01), Grondahl
patent: 3790870 (1974-02-01), Mitchell
patent: 3890161 (1975-06-01), Brown
patent: 3993411 (1976-11-01), Babcock et al.
patent: 5108562 (1992-04-01), Duke et al.
patent: 5128008 (1992-07-01), Chen et al.
patent: 5225034 (1993-07-01), Yu et al.
patent: 5225711 (1993-07-01), Chang et al.
patent: 5401714 (1995-03-01), Chaudhari et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5714418 (1998-02-01), Bai et al.
patent: 6037257 (2000-03-01), Chiang et al.
patent: 6066560 (2000-05-01), Yakura
Boher et al., Thin Solid Films, No. 174, 1989, pp. 91-98 1989.*
Gwynne, Peter, “Back To The Future: Copper Comes Of Age”, IBM Research, No. 4, 1997, pp. 17-21.
“Solid state”, Technology 1998 Analysis & Forecast, IEEE Spectrum, Jan. 1998, pp. 23-24.
Ramo, Joshua C., “Chips Ahoy”, Time, Oct. 6, 1997, p. 72.
“Back to the Future: Copper Comes of Age”, IBM Research Magazine, 1997, Issue No. 4.
Boher et al., “Diode R.F. Sputtering of Copper and Copper Oxide Thin Films and Multilayers”, Thin Solid Films, 174 (Mar. 1989), pp. 91-98.
Bowers Charles
Lee Hsien-Ming
LSI Logic Corporation
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