Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-05-13
2004-08-10
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S736000, C257S739000, C257S749000, C257S773000, C257S777000, C257S787000
Reexamination Certificate
active
06774499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a non-leaded semiconductor package and method of fabricating the same, which can be used for the fabrication of a non-leaded type of semiconductor package, such as a CQFN (Carrierless Quad Flat No-lead) package.
2. Description of Related Art
U.S. Pat. No. 5,830,800 “PACKAGING METHOD FOR A BALL GRID ARRAY INTEGRATED CIRCUIT WITHOUT UTILIZING A BASE PLATE” discloses an advanced type of semiconductor packaging technology called CQFN (Carrierless Quad Flat No-lead), which is used in the semiconductor industry for the fabrication of small size semiconductor packages.
FIG. 4
is a schematic diagram showing the structure of a CQFN package. As shown, this CQFN package is characterized by the provision of non-leaded external connecting pads
20
on the bottom surface of the encapsulation body for external electrical connection with a printed circuit board. Since these pads are non-protruding beyond the encapsulation body, the resulted package
10
appears to be non-leaded and therefore is considerably made more compact in size than leaded-type of semiconductor packages.
In the foregoing CQFN package, the internal packaged chip is typically electrically connected to the non-leaded external connecting pads by means of bonding wires
12
. Moreover, conventional CQFN package structures are typically constructed on a metal plate, i.e., the packaged chip
30
is mounted on the front side of a metal plate while the non-leaded external connecting pads are arranged at the front side of the metal plate. However, as the semiconductor fabrication technology has advanced to the next level of downsizing, such as below 0.5 mm, it becomes highly difficult to use the wire bonding technology for internal interconnecting of the packaged chip
30
with the non-leaded external connecting pads in the CQFN package due to the restriction in wire loop height. Moreover, it also becomes highly difficult and costly to fabricate a smaller metal plate for the CQFN package. Therefore, in view of the foregoing problems of prior art, there exists a need in the semiconductor industry for a new semiconductor packaging technology that can be used for the fabrication of a CQFN semiconductor package without the use of wire bonding technology for the fabrication of the CQFN packages.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a non-leaded semiconductor packaging technology which can be used for the fabrication of a CQFN semiconductor package without the use of bonding wires for internal electrical connections.
The proposed semiconductor packaging technology is characterized by the use of a plate as provisional chip carrier during fabrication and by the use of RDL (Redistribution Layer) technology to provide internal electrical interconnections between the I/O pads of the packaged chip and the non-leaded external electrical contacts. These features allow the fabrication of the CQFN package to be implemented without the use of bonding wires for internal electrical connections and without the use of substrate as a permanent chip carrier.
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Clark Jasmine
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
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