Non-Continuous encapsulation layer for MIM capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S238000, C438S386000, C438S399000, C438S250000, C438S393000, C257S532000, C257S535000, C257S296000, C257S300000

Reexamination Certificate

active

06913965

ABSTRACT:
The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

REFERENCES:
patent: 6144051 (2000-11-01), Nishimura et al.
patent: 6284590 (2001-09-01), Cha et al.
patent: 6319767 (2001-11-01), Cha et al.
patent: 6344964 (2002-02-01), Adler
patent: 6430028 (2002-08-01), Kar-Roy et al.
patent: 2002/0068431 (2002-06-01), Petrarca et al.
patent: 2003/0027386 (2003-02-01), Lee

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